vhdl错误：靠近“梯子”：（vcom-1576）预计为IS。 ＃

Question

在“梯子”附近：（vcom-1576）预计为IS。 在“梯子”附近：（vcom-1576）预期为IS。 在“梯子”附近：（vcom-1576）预期为IS。 在“梯子”附近：（vcom-1576）预期为IS。 靠近“梯子”：（vcom-1576）期望是IS。

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;



ENTITY tb ladder IS

END tb ladder;
ARCHITECTURE behavior OF tb ladder  IS

COMPONENT ladder

PORT(A : IN std_logic_vector(3 downto 0);
     B : IN std_logic_vector(3 downto 0);
     CIN : IN std_logic;
     SUM : OUT std_logic_vector(3 downto 0);
     COUT : OUT std_logic
     );
END COMPONENT;


signal A : std_logic_vector(3 downto 0) := (others => '0100');
signal B : std_logic_vector(3 downto 0) := (others => '1001');
signal CIN : std_logic := '0';
signal SUM : std_logic_vector(3 downto 0);
signal COUT : std_logic;


BEGIN


uut: ladder PORT MAP (
A => A,
B => B,
CIN => CIN,
SUM => SUM,
COUT => COUT
);

stim_proc: process begin

wait for 2 ns;
A <= "0100";
wait for 5 ns;
B <= "1001";
wait for 3 ns;
CIN <= "O";

wait for 2 ns;
A <= "1101";
wait for 5 ns;
B <= "0011";
wait for 3 ns;
CIN <= "1";

wait for 2 ns;
A <= "0100";
wait for 5 ns;
B <= "0110";
wait for 3 ns;
CIN <= "0";

wait for 2 ns;
A <= "1101";
wait for 5 ns;
B <= "1100";
wait for 3 ns;
CIN <= "1";

wait for 2 ns;
A <= "0100";
wait for 5 ns;
B <= "1001";
wait for 3 ns;
CIN <= "0";

end process;

END ;

所以，我的错误是：

  

错误：C：\ Modeltech_pe_edu_10.4a \ examples \ tbladder.vhd（7）：靠近“梯子”：（vcom-1576）期望IS。

如果您知道我的错误，请为我更正我的代码。

Answer 1

实体名称必须是一个单词。您有tb ladder，编译器期望后面跟着一个IS的单词。使用tb_ladder之类的名称来解决此问题。