Question

我正在模拟CPU，我正在使用高级仿真工具。 SystemC是用于这些目的的良好资源。我正在使用两个模块：

数据路径
内存

CPU数据路径被建模为唯一的高级实体，但是以下代码肯定会比任何其他解释更好：

以下是datapath.hpp

SC_MODULE(DataPath) {
    sc_in_clk clk;
    sc_in<bool> rst;
    ///
    /// Outgoing data from memory.
    ///
    sc_in<w32> mem_data;
    ///
    /// Memory read enable control signal.
    ///
    sc_out<sc_logic> mem_ctr_memreadenable;
    ///
    /// Memory write enable control signal.
    ///
    sc_out<sc_logic> mem_ctr_memwriteenable;
    ///
    /// Data to be written in memory.
    ///
    sc_out<w32> mem_dataw; //w32 is sc_lv<32>
    ///
    /// Address in mem to read and write.
    ///
    sc_out<memaddr> mem_addr;
    ///
    /// Program counter.
    ///
    sc_signal<w32> pc;
    ///
    /// State signal.
    ///
    sc_signal<int> cu_state;
    ///
    /// Other internal signals mapping registers' value.
    /// ...

    // Defining process functions
    ///
    /// Clock driven process to change state.
    ///
    void state_process();
    ///
    /// State driven process to apply control signals.
    ///
    void control_process();

    // Constructors
    SC_CTOR(DataPath) {
        // Defining first process
        SC_CTHREAD(state_process, clk.neg());
        reset_signal_is(this->rst, true);
        // Defining second process
        SC_METHOD(control_process);
        sensitive << (this->cu_state) << (this->rst);
    }

    // Defining general functions
    void reset_signals();
};

以下是datapath.cpp

void DataPath::state_process() {
    // Useful variables
    w32 ir_value; /* Placing here IR register value */
    // Initialization phase
    this->cu_state.write(StateFetch); /* StateFetch is a constant */
    wait(); /* Wait next clock fall edge */
    // Cycling
    for (;;) {
        // Checking state
        switch (this->cu_state.read()) { // Basing on state, let's change the next one
        case StateFetch: /* FETCH */
            this->cu_state.write(StateDecode); /* Transition to DECODE */
            break;
        case StateDecode: /* DECODE */
            // Doing decode
            break;
        case StateExecR: /* EXEC R */
            // For every state, manage transition to the next state
            break;
        //...
        //...
        default: /* Possible not recognized state */
            this->cu_state.write(StateFetch); /* Come back to fetch */
        } /* switch */
        // After doing, wait for the next clock fall edge
        wait();
    } /* for */
} /* function */

// State driven process for managing signal assignment
// This is a method process
void DataPath::control_process() {
    // If reset signal is up then CU must be resetted
    if (this->rst.read()) {
        // Reset
        this->reset_signals(); /* Initializing signals */
    } else {
        // No Reset
        // Switching on state
        switch (this->cu_state.read()) {
        case StateFetch: /* FETCH */
            // Managing memory address and instruction fetch to place in IR
            this->mem_ctr_memreadenable.write(logic_sgm_1); /* Enabling memory to be read */
            this->mem_ctr_memwriteenable.write(logic_sgm_0); /* Disabling memory from being written */
            std::cout << "Entering fetch, memread=" << this->mem_ctr_memreadenable.read() << " memwrite=" << this->mem_ctr_memreadenable.read() << std::endl;
            // Here I read from memory and get the instruction with some code that you do not need to worry about because my problem occurs HERE ###
            break;
        case kCUStateDecode: /* DECODE */
            // ...
            break;
        //...
        //...
        default: /* Unrecognized */
            newpc = "00000000000000000000000000000000";
        } /* state switch */
    } /* rst if */
} /* function */

// Resetting signals
void DataPath::reset_signals() {
    // Out signals
    this->mem_ctr_memreadenable.write(logic_sgm_1);
    this->mem_ctr_memwriteenable.write(logic_sgm_0);
}

正如你所看到的，我们有一个处理cpu转换（改变状态）的时钟驱动进程和一个为cpu设置信号的状态驱动进程。

我的问题是，当我到达###时，我希望指令被内存释放（你看不到指令但它们是正确的，内存组件使用进出的信号连接到数据路径你可以看到在hpp文件中）。内存获取"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"，因为mem_ctr_memreadenable和mem_ctr_memwriteenable都设置为'0'。编写内存模块是为了成为即时组件。它是使用SC_METHOD编写的，sensitive在输入信号上定义（包括读使能和写使能）。当"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"信号为mem_ctr_memreadenable时，内存组件会'0'。

为什么'0'？我重置信号并将该信号设置为'1'。我不明白为什么我继续使用'0'读取使能信号。

你能帮帮我吗？三江源。

Answer 1

我不是SystemC大师，但看起来它可能是一个类似的问题，因为在至少一个delta周期已经过去之前信号不会更新的常见VHDL问题：

this->mem_ctr_memreadenable.write(logic_sgm_1); /* Enabling memory to be read */
this->mem_ctr_memwriteenable.write(logic_sgm_0); /* Disabling memory from being written */

我的猜测：这两行和下一行之间没有时间过去了：

std::cout << "Entering fetch, memread=" << this->mem_ctr_memreadenable.read() << " memwrite=" << this->mem_ctr_memreadenable.read() << std::endl;

因此内存尚未见到读取信号的变化。顺便说一句，如果其中一个read()来电附加到mem_ctr_memwriteenable - 两者似乎都可以重新申请了吗？

如果你：

wait(1, SC_NS);

在这两点之间，是否会改善问题？

Answer 2

要与您应使用的内存模块进行零时间同步等待（SC_ZERO_TIME）; //等一个delta周期不要在你的定时模拟中引入任意的时间消耗。这也会强制您将control_process升级为SC_THREAD

SystemC仿真应用程序中的问题处理信号

2 个答案: