Question

我有采用256 BGA封装的Lattice iCE40 HX8K FPGA。我想使用一个可用的PLL模块将37MHz的外部时钟频率转换为74MHz的FPGA内部使用的内部时钟。

我在IceCube2中使用了“配置PLL模块”，并使用了以下配置： -PLL类型部分： -由PLL输出驱动的GlobalNetworks：1； -专用时钟垫； -PLL工作模式： -无补偿模式； -其他延迟设置：否； - 频率：输入-37MHz; -输出-74MHz; -其他-没有选择；

然后，我得到了两个VHDL文件-SO_pll.vhd和SO_pll_inst.vhd。我有Design.vhd文件，该代码应该放在其中。如果我正确理解Lattice文档，则需要指定Design.vhd（它的实体）是我执行的顶层模块。我需要包括我做了IceCube2中设计文件列表中的SO_pll.vhd。最后-我需要使用SO_pll_inst.vhd中提供的模板，通过将PLL信号端口映射到Design.vhd中的信号，在我的主代码中实例化PLL。麻烦来了-该怎么办？

---Design.vhd---

library IEEE;
use IEEE.std_logic_1164.all;

entity Design is
port(
      I_CLK: in std_logic
    );
end entity Design;


    architecture RTL of Design is

signal S_CLK : std_logic;
signal S_RESET : std_logic;

begin

SO_pll_inst: SO_pll
port map(
          REFERENCECLK => I_CLK,
          PLLOUTCORE => open,
          PLLOUTGLOBAL => S_CLK,
          RESET => S_RESET
        );

end RTL;


    ---SO_pll_inst.vhd---Generated by IceCube2

    SO_pll_inst: SO_pll
    port map(
          REFERENCECLK => ,
          PLLOUTCORE => ,
          PLLOUTGLOBAL => ,
          RESET => 
            );



---SO_pll.vhd---Generated by IceCube2
library IEEE;
use IEEE.std_logic_1164.all;

entity SO_pll is
port(
      REFERENCECLK: in std_logic;
      RESET: in std_logic;
      PLLOUTCORE: out std_logic;
      PLLOUTGLOBAL: out std_logic
    );
end entity SO_pll;

architecture BEHAVIOR of SO_pll is
signal openwire : std_logic;
signal openwirebus : std_logic_vector (7 downto 0);
component SB_PLL40_CORE
  generic (
        --- Feedback
FEEDBACK_PATH : string := "SIMPLE"; -- String (simple, delay, 
phase_and_delay, external)
DELAY_ADJUSTMENT_MODE_FEEDBACK   : string := "FIXED"; 
DELAY_ADJUSTMENT_MODE_RELATIVE   : string := "FIXED"; 
SHIFTREG_DIV_MODE : bit_vector(1 downto 0)  := "00"; 
--  0-->Divide by 4, 1-->Divide by 7, 3 -->Divide by 5  
FDA_FEEDBACK    : bit_vector(3 downto 0)    := "0000"; 
--  Integer (0-15). 
FDA_RELATIVE    : bit_vector(3 downto 0)    := "0000";  
--  Integer (0-15).
PLLOUT_SELECT   : string := "GENCLK";

--- Use the spread sheet to populate the values below
DIVF    : bit_vector(6 downto 0); 
-- Determine a good default value
DIVR    : bit_vector(3 downto 0);
-- Determine a good default value
DIVQ    : bit_vector(2 downto 0);
-- Determine a good default value
FILTER_RANGE    : bit_vector(2 downto 0);
-- Determine a good default value

--- Additional C-Bits
ENABLE_ICEGATE  : bit := '0';

--- Test Mode Parameter 
TEST_MODE   : bit := '0';
EXTERNAL_DIVIDE_FACTOR  : integer := 1
-- Not Used by model, Added for PLL config GUI
   );
port (
    REFERENCECLK    : in std_logic;    -- Driven by core logic
    PLLOUTCORE  : out std_logic;   -- PLL output to core logic
    PLLOUTGLOBAL    : out std_logic;   -- PLL output to global network
    EXTFEEDBACK : in std_logic;    -- Driven by core logic
    DYNAMICDELAY    : in std_logic_vector (7 downto 0); -- Driven by core 
logic
    LOCK        : out std_logic;    -- Output of PLL
    BYPASS      : in std_logic;     -- Driven by core logic
    RESETB      : in std_logic;     -- Driven by core logic
    LATCHINPUTVALUE : in std_logic;     -- iCEGate Signal
    -- Test Pins
    SDO     : out std_logic;    -- Output of PLL
    SDI     : in std_logic;     -- Driven by core logic
    SCLK        : in std_logic      -- Driven by core logic
   );
end component;
begin
SO_pll_inst: SB_PLL40_CORE
-- Fin=37, Fout=74
generic map(
         DIVR => "0000",
         DIVF => "0001111",
         DIVQ => "011",
         FILTER_RANGE => "011",
         FEEDBACK_PATH => "SIMPLE",
         DELAY_ADJUSTMENT_MODE_FEEDBACK => "FIXED",
         FDA_FEEDBACK => "0000",
         DELAY_ADJUSTMENT_MODE_RELATIVE => "FIXED",
         FDA_RELATIVE => "0000",
         SHIFTREG_DIV_MODE => "00",
         PLLOUT_SELECT => "GENCLK",
         ENABLE_ICEGATE => '0'
       )
port map(
      REFERENCECLK => REFERENCECLK,
      PLLOUTCORE => PLLOUTCORE,
      PLLOUTGLOBAL => PLLOUTGLOBAL,
      EXTFEEDBACK => openwire,
      DYNAMICDELAY => openwirebus,
      RESETB => RESET,
      BYPASS => '0',
      LATCHINPUTVALUE => openwire,
      LOCK => open,
      SDI => openwire,
      SDO => open,
      SCLK => openwire
    );

end BEHAVIOR;

我刚刚将Design.vhd和SO_pll.vhd添加到设计文件列表中。如果我使用莱迪思LSE运行综合，则合成成功，但是放置器报告显示已使用0/2 PLL。如果我运行带有Synplify Pro放置器的Synthesys报告显示使用了1/2 PLL，但是由于没有映射信号，我真的不能使用它。

当我从SO_pll_inst.vhd获取模板并将其放置在Design.vhd的体系结构内部时，我收到错误消息： “错误-综合：design.vhd（19）：未声明so_pll。VHDL-1241” 好吧，显然我缺少了一些东西。如果它是模板，那么我希望只是映射我的信号并使其运行。但不是。我是在做错事，还是...我在做错事:)请帮忙。

Answer 1

好笑-我发布了问题，并发布了答案！ :)可以了：

<?xml version="1.0" encoding="utf-8"?>
<androidx.drawerlayout.widget.DrawerLayout xmlns:android="http://schemas.android.com/apk/res/android"
    xmlns:app="http://schemas.android.com/apk/res-auto"
    android:id="@+id/drawer_layout"
    android:layout_width="match_parent"
    android:layout_height="match_parent"
    android:fitsSystemWindows="true">

    <androidx.constraintlayout.widget.ConstraintLayout
        android:id="@+id/content_frame"
        android:layout_width="match_parent"
        android:layout_height="match_parent">

        <androidx.appcompat.widget.Toolbar
            android:id="@+id/toolbar"
            android:layout_width="match_parent"
            android:layout_height="?attr/actionBarSize"
            android:background="?attr/colorPrimary"
            android:theme="@style/ThemeOverlay.AppCompat.Dark.ActionBar"
            app:titleTextAppearance="@style/Toolbar.TitleText"
            app:layout_constraintTop_toTopOf="parent"
            app:layout_constraintStart_toStartOf="parent"
            app:layout_constraintEnd_toEndOf="parent"/>

        <ScrollView
            android:id="@+id/fragment_container"
            android:layout_width="match_parent"
            android:layout_height="match_parent"
            android:layout_marginTop="?attr/actionBarSize"
            android:fillViewport="true"
            app:layout_constraintTop_toBottomOf="@id/toolbar"
            app:layout_constraintStart_toStartOf="parent"
            app:layout_constraintEnd_toEndOf="parent"
            app:layout_constraintBottom_toBottomOf="parent">

            <!-- Content of fragment_main.xml -->
            <LinearLayout
                xmlns:tools="http://schemas.android.com/tools"
                android:layout_width="match_parent"
                android:layout_height="wrap_content"
                android:orientation="vertical"
                android:gravity="center"
                tools:context=".MainFragment">

                <androidx.constraintlayout.widget.ConstraintLayout
                    android:layout_width="wrap_content"
                    android:layout_height="match_parent"
                    android:layout_gravity="center"
                    android:paddingTop="30dp"
                    android:paddingBottom="30dp">


                    <ImageButton
                        android:id="@+id/overlay_button"
                        android:layout_width="0dp"
                        android:layout_height="0dp"
                        android:background="@null"
                        android:contentDescription="@string/start_speedometer"
                        android:scaleType="fitCenter"
                        android:src="@drawable/btn_circle_green"
                        app:layout_constraintDimensionRatio="1:1"
                        app:layout_constraintTop_toTopOf="parent"
                        app:layout_constraintBottom_toBottomOf="parent"
                        app:layout_constraintStart_toStartOf="parent"
                        app:layout_constraintEnd_toEndOf="parent"/>

                    <TextView
                        android:id="@+id/overlay_button_text"
                        android:layout_width="wrap_content"
                        android:layout_height="wrap_content"
                        android:clickable="false"
                        android:text="@string/start_speedometer"
                        android:textColor="@color/white"
                        android:textSize="40sp"
                        app:layout_constraintTop_toTopOf="parent"
                        app:layout_constraintBottom_toBottomOf="parent"
                        app:layout_constraintStart_toStartOf="parent"
                        app:layout_constraintEnd_toEndOf="parent"/>

                </androidx.constraintlayout.widget.ConstraintLayout>

            </LinearLayout>

        </ScrollView>

    </androidx.constraintlayout.widget.ConstraintLayout>

    <com.google.android.material.navigation.NavigationView
        android:id="@+id/nav_view"
        android:layout_width="wrap_content"
        android:layout_height="match_parent"
        android:layout_gravity="start"
        android:fitsSystemWindows="false"
        app:menu="@menu/nav_drawer_view"
        app:headerLayout="@layout/nav_drawer_header"
        app:itemIconTint="@drawable/nav_drawer_item_icon_color"
        app:itemTextColor="@drawable/nav_drawer_item_text_color" />

</androidx.drawerlayout.widget.DrawerLayout>

因此，从上方的文件中可以明显看出，密钥的实例化是PLL文件的实体。我在PLL文件中指定的实体名称之前缺少关键字“实体”。不出所料，我做错了。

莱迪思iCE40的故障实例化PLL

1 个答案: