Question

这是我到目前为止所知道的代码，我的代码中的问题是出现我16错误。

我不知道我的代码是否正确，所以请帮助我如何在EDA游乐场中解决此问题。当我运行代码时，对于所有D和Q，都会出现此错误“端口映射中的实际参数类型与正式端口'D'的类型不匹配”。另外，我必须通过d触发器将其执行4倍的处理，因此必须将前4位传输到其他4位

有人可以帮助我了解如何使用串行和并行触发器来传输位。请使用VHDL语言新手，我需要帮助

    -- Code your design here
    library IEEE;
    use IEEE.std_logic_1164.all;

     -- declaration for d flip-flop
     entity D_FF is
     PORT( D : in std_logic_vector(7 downto 0); --input 
           s :in std_logic; --shift/load 
           CLOCK: in std_logic;
           Q: out std_logic_vector(7 downto 0));--output for each d flip-flop
      end D_FF;

     architecture behavioral of D_FF is
     begin
     --8 d flip flop that transfer the bit 
    D_ff: entity work.D_FF port map(D(0),s,CLOCK,Q(0));
    D_ff1: entity work.D_FF port map(D(1),s,CLOCK,Q(1));
    D_ff2: entity work.D_FF port map(D(2),s,CLOCK,Q(2));
    D_ff3: entity work.D_FF port map(D(3),s,CLOCK,Q(3));
    D_ff4: entity work.D_FF port map(D(4),s,CLOCK,Q(4));
    D_ff5: entity work.D_FF port map(D(5),s,CLOCK,Q(5));
    D_ff6: entity work.D_FF port map(D(6),s,CLOCK,Q(6));
    D_ff7: entity work.D_FF port map(D(7),s,CLOCK,Q(7));
    -- process for shift/load
    process(CLOCK,D,s)
    begin 
        -- if shift/load is 1 then Q is equal D
        if s ='1' then 
            Q<=D;
        end if;
    end process;
    end behavioral;

     ------------------------------
    -- testbench
     ------------------------------
     -- library
    library ieee;
    use ieee. std_logic_1164.all;


    entity testbench is 
    -- empty entity
    end testbench;
    -----------------------------
    architecture tb of testbench is -- testbench 
    -- architecture  -- REDUNDANT transcription error?

     -- component declaration for D flip-flop
     component D_FF is
     PORT( D : in std_logic_vector(7 downto 0);--input
           s :in std_logic;--shift/load
           CLOCK: in std_logic;
           Q: out std_logic_vector(7 downto 0));--output for each d flip-flop
      end component;

      -- signals 
      signal D_s: std_logic_vector(7 downto 0);-- signals for entity i/o
      signal s_s: std_logic; -- signal for shift/load
      signal CLOCK_s: std_logic;
      signal Q_s: std_logic_vector(7 downto 0);-- signals for entity i/o
       begin

   -- design under test instantiation
     dut: D_FF 
      port map (
        D     => D_s, --D is equal with D_s singal 
        s     => s_s, --s is equal with s_s signal
        CLOCK => CLOCK_s, --CLOCK is equal with CLOCK_s signal
        Q     => Q_s --Q is equal with Q_s signal
      );  

     stimProcess: process 
     --stimulus generator
      begin    
        -- the bit first bit must transfer 
        D_s <="01100000";
        s_s <= '0'; -- shift/load
        wait until CLOCK_s = '1' and CLOCK_s'event;

      end process stimProcess;                                  
      -- without sensitivity list
      end tb;`enter code here`

同步电路，使用D触发器以串行方式将二进制文件从4位寄存器传输到另一个4位寄存器

0 个答案: