Question

我是Verilog HDL的新手，并试图将我的VHDL代码转换为Verilog HDL代码，但由于数据结构确实有所不同，因此仍停留在数据结构上。由于我已经习惯了高级编程语言，因此我无法完全围绕这种编码进行

   ---------------------/ PACKAGE SECTION /-------------------— 

 library ieee; 
 use ieee.std_logic_1164.all; 
 use ieee.numeric_std.all; 

 package array_types is 
  type array_t is array(15 downto 0) of natural range 0 to 15; 
 end array_types; 

 —-----------------/ END PACKAGE SECTION /-----------------— 

 library ieee; 
 use ieee.std_logic_1164.all; 
 use ieee.numeric_std.all; 
 use work.array_types.all; 
 use ieee.std_logic_unsigned.all; 

 entity countingSort is 
  port( 
   signal clk : in std_logic; 
   signal in_array : in array_t; 
   signal out_array : out array_t; 
   signal out_i : out integer; 
   signal out_j : out integer; 
   signal out_k : out integer; 
   signal out_is_c : out std_logic; 
   signal out_count : out array_t 
  ); 
 end countingSort; 

 architecture arch of countingSort is 

  signal count_array : array_t; 
  signal is_counted : std_logic := '0'; 
  signal i : natural range 0 to 15 := 0; 
  signal j : integer := 0; 
  signal k : integer := 0; 
  signal adr : integer := 0; 

 begin 

  process(clk) 
  begin 
   out_i <= i; 
   out_j <= j; 
   out_k <= k; 
   out_is_c <= is_counted; 
   out_count <= count_array; 
   if rising_edge(clk) then 
    if is_counted = '1' then 
     if j < 16 then 
      if k < count_array(j) then 
       out_array(adr) <= j; 
       k <= k + 1; 
       adr <= adr + 1; 
      else 
       j <= j + 1; 
       k <= 0; 
      end if; 
     end if; 
    else 
     count_array(in_array(i)) <= count_array(in_array(i)) + 1; 
     i <= i + 1; 
     if i = 15 then 
      is_counted <= '1'; 
     else 
      is_counted <= '0'; 
     end if; 
    end if; 
   end if; 
  end process; 

 end arch;

执行这种算法的最佳方法是什么？有一种简单的方法可以翻译此类应用程序吗？

如何在Verilog HDL中进行计数排序？

0 个答案: