Question

我要在Verilog中级联几个缓冲区。我的示例如下，我定义了16个在结构定义中级联的缓冲区：

BUFX12 BUF01(dummy_wire[1],N62878);
BUFX12 BUF02(dummy_wire[2],dummy_wire[1]);
BUFX12 BUF03(dummy_wire[3],dummy_wire[2]);
BUFX12 BUF04(dummy_wire[4],dummy_wire[3]);
BUFX12 BUF05(dummy_wire[5],dummy_wire[4]);
BUFX12 BUF06(dummy_wire[6],dummy_wire[5]);
BUFX12 BUF07(dummy_wire[7],dummy_wire[6]);
BUFX12 BUF08(dummy_wire[8],dummy_wire[7]);
BUFX12 BUF09(dummy_wire[9],dummy_wire[8]);
BUFX12 BUF10(dummy_wire[10],dummy_wire[9]);
BUFX12 BUF11(dummy_wire[11],dummy_wire[10]);
BUFX12 BUF12(dummy_wire[12],dummy_wire[11]);
BUFX12 BUF13(dummy_wire[13],dummy_wire[12]);
BUFX12 BUF14(dummy_wire[14],dummy_wire[13]);
BUFX12 BUF15(dummy_wire[15],dummy_wire[14]);

由于我要在测试设计中更改缓冲区的数量，因此我正在寻找诸如for-loop之类的语法以自动格式实现以下结构，但我不知道正确的结构。我想知道是否可能，正确的语法是什么。此外，最好将实现命名为实例。

Answer 1

使用实例数组：

wire [15:1] other = {dummy_wire[14:1], N62878};
BUFX12 BUF [15:1] (dummy_wire, other);

Answer 2

如果愿意，可以使用generate循环，但是@toolic提供的实例解决方案数组更紧凑：

$pagination_number = 1; //Default pagination number, change as per pagination number
$total_posts = 30;
$posts_per_page = 5;
//This will change based on pagination number, it indicate how many post to skip
$offset = ($pagination_number - 1) * $posts_per_page;  

$data = WP_Query(array(
'post_type' => 'staff_bios',
'posts_per_page' => $posts_per_page,
's' => $data['term'],
'orderby' => 'title',
'order' => 'asc',
'offset' => $offset,
));

$total_pagination = $total_posts/$posts_per_page; //(1, 2, 3 ,4 , 5, ....)

//LOOP THGOUGH DATA

Verilog-2005放宽了有关assign dummy_wire[0] = N62878; generate genvar g; for (g=1; g<16; g=g+1) begin : in_Verilog_2001_you_need_this_and_it_needs_a_name BUFX12 BUF(dummy_wire[g],dummy_wire[g-1]); end endgenerate的规则。在Verilog-2005中这是合法的：

generate

在SystemVerilog中，您可以将其整理得更多一点：

  assign dummy_wire[0] = N62878;

  genvar g;
  for (g=1; g<16; g=g+1)
    BUFX12 BUF(dummy_wire[g],dummy_wire[g-1]);

但就我个人而言，我喜欢Verilog-2001版本：它更明确。

MCVE ：

  assign dummy_wire[0] = N62878;

  for (genvar g=1; g<16; g++)
    BUFX12 BUF(dummy_wire[g],dummy_wire[g-1]);

https://www.edaplayground.com/x/YWw

是否可以在结构性Verilog中重复门？

2 个答案: