Question

我正在尝试在系统Verilog中学习阵列约简技术。写下以下模块：

module main;

localparam [7:0]PARAM_ARR0[3:0] = '{8'h1,8'h3,8'h4,8'h0};
localparam [3:0]PARAM_ARR1[7:0] = '{4'h3,4'h2,4'h2,4'h2,4'h1,4'h1,4'h1,4'h1};

int s = 0;
logic [7:0]arr0[3:0] = '{8'h1,8'h3,8'h4,8'h0};
logic [3:0]arr1[7:0] = '{4'h3,4'h2,4'h2,4'h2,4'h1,4'h1,4'h1,4'h1};

initial begin

//s = int'(PARAM_ARR0.sum() with (item.index<int'(PARAM_ARR1[0])?item:0));
//$display("sum0 = %0d",s);
//s = int'(PARAM_ARR0.sum() with (item.index<int'(PARAM_ARR1[4])?item:0));
//$display("sum1 = %0d",s);
s = int'(arr0.sum() with (item.index<int'(arr1[0])?item:0));
$display("sum0 = %0d",s);
s = int'(arr0.sum() with (item.index<int'(arr1[4])?item:0));
$display("sum1 = %0d",s);
s = int'(arr0.sum() with (item.index<int'(arr1[7])?item:0));
$display("sum2 = %0d",s);
end

endmodule

如果我取消注释初始（在2D参数数组上的数组缩减）后的前4行，则VCS会引发如下编译错误。数组方法不适用于参数数组吗？

    Error-[XMRE] Cross-module reference resolution error
    ../../test_param_array_sum.sv, 10
      Error found while trying to resolve cross-module reference.
      token 'sum'.  Originating module 'main'.
      Source info: PARAM_ARR0.sum(item) with (((item.index < int'(4'b1))
      ? item : 0))



    Error-[IND] Identifier not declared
    ../../test_param_array_sum.sv, 10
      Identifier 'item' has not been declared yet. If this error is not expected, 
      please check if you have set `default_nettype to none.

另一个疑问是，当我如上所述在VCS中模拟代码时，得到的结果如下：

sum0 = 1
sum1 = 4
sum2 = 8

我期望结果分别为0、4和7。因为我试图获取arr0中索引分别小于arr1 [0]（1），arr1 [4]（2），arr1 [7]（3）的所有元素的总和。

谢谢

Answer 1

这对Questa 2019.2。您可能需要与您的EDA AE讨论发生了什么问题。 Serge关于使用动态数组的建议有效：https://www.edaplayground.com/x/26RL

另外，看起来您的代码正在提供您在Questa中预期的结果。

# Loading sv_std.std
# Loading work.main(fast)
# run -all
# sum0 = 0
# sum1 = 4
# sum0 = 0
# sum1 = 4
# sum2 = 7
#  quit -f
# End time: 11:17:11 on May 23,2019, Elapsed time: 0:00:21
# Errors: 0, Warnings: 0

系统Verilog数组减少陷阱和参数数组

1 个答案: