VHDL预加载带有MIF文件的RAM存储器

时间:2019-05-14 05:05:24

标签: vhdl ram modelsim quartus

我正在尝试在VHDL中实现内存,并且在DE2板上测试内存时,我想用生成的值预加载内存。我首先尝试通过读取文本文件来完成此操作,但由于无法将文本文件加载到FPGA板上而无法正常工作。所以我转向了mif文件。但是,我不知道如何获取vhdl / quartus ii以将生成的MIF文件与创建的RAM相关联。

我也尝试过使用1端口RAM LPM,但是因为它既为读取又为写入提供时钟,这导致它不能足够快地提供有用的数据。

下面是我创建的RAM的代码:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;

entity instruction_memory is
    port (
        input_address : in std_logic_vector(31 downto 0);
        opcode : out std_logic_vector(31 downto 0)
    );
end instruction_memory;

architecture archInstruction_Memory of instruction_memory is
    subtype word_t  is std_logic_vector(31 downto 0);
    type    ram_t   is array(0 to 4095) of Reichman_word_t;

    impure function ReadMemFile(FileName : STRING) return ram_t is
        file FileHandle       : TEXT open READ_MODE is FileName;
        variable CurrentLine  : LINE;
        variable TempWord     : bit_vector(31 downto 0);
        variable Result       : ram_t    := (others => (others => '0'));

        begin
           for i in 0 to 4095 loop
                exit when endfile(FileHandle);
                readline(FileHandle, CurrentLine);
                read(CurrentLine, TempWord);
                Result(i) := to_stdlogicvector(TempWord);
            end loop;

            return Result;
        end function;

        signal ram    : ram_t    := ReadMemFile("instructions_memory.txt");
        attribute ram_init_file : string;
        attribute ram_init_file of ram : signal is "instructions_memory.mif";


begin 
    opcode <= ram(to_integer(unsigned(input_address(31 downto 0))));
end archInstruction_Memory;

如何获取它预加载.mif文件中的数据,以便在DE2板上进行测试时显示它使用了这些值?

1 个答案:

答案 0 :(得分:1)

我正在使用tcl脚本将二进制数据(代码)转换为可用于生成ROM的VHDL常量:

package require cmdline

post_message "embed_m68k.tcl"

exec /bin/bash -c "(cd m68k; make)"
set binfile m68k/simple.bin
set fp [open $binfile r]
fconfigure $fp -translation binary
set bindata [read $fp]
close $fp

set filename simple.vhd

set date [clock format [clock seconds] -format { %a, %Y-%m-%d, %H:%M }]
set file [open $filename w]
set script [info script]

puts $file "library ieee;"
puts $file "use ieee.std_logic_1164.all;"
puts $file ""
puts $file "    -- VHDL representation of $binfile"
puts $file "    -- generated by $script on $date"
puts $file "    -- m68k executable as preloaded RAM contents"
puts $file ""
puts $file "package m68k_binary is"
puts $file "    subtype ubyte is std_logic_vector(7 downto 0);"
puts $file "    type ubyte_array is array (natural range <>) of ubyte;"
puts $file ""
puts $file "    constant m68k_binary    : ubyte_array :="
puts $file "    ("
puts -nonewline $file "        "
set len [string length $bindata]
for {set i 0} {$i < $len} {incr i} {
    set char [string index $bindata $i]
    binary scan $char H2 byte
    puts -nonewline $file "x\""
    puts -nonewline $file $byte
    puts -nonewline $file "\""
    if { ! ([expr $i + 1] == $len) } {
        puts -nonewline $file ", "
    }
    if { [expr ($i + 1) % 8] == 0 } {
        puts $file ""
        puts -nonewline $file "        "
    }
}
puts $file ""
puts $file "    );"
puts $file "end package m68k_binary;"
close $file

您可以使用.qsf中的PRE_FLOW_SCRIPT_FILE变量轻松地将脚本包含在Quartus工作流程中:

set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:precmd.tcl"

PRE_FLOW_SCRIPT_FILE将在综合过程开始时自动执行。只需将生成的.vhd文件包含到您的项目中即可。