是否在VHDL的有限状态机中进行连续测试？

Question

我的组件从RAM内存中读取，进行一些计算并写回到内存中。我编写了多个具有不同RAM值的测试台，这些测试台已成功测试。问题是我总是必须每次都分别运行测试平台。

我想知道是否可能有一个带有不同RAMS的测试台，并且只运行一个测试台。因此，一个带有RAM的测试一旦完成，便会使用另一个RAM。这还将测试我的FSM在写入内存后是否返回到空闲状态，然后再读取另一个RAM。

这是模板测试台：

entity project is
end project;

architecture project of project is
....
....
....
....

type ram_type is array (65535 downto 0) of std_logic_vector(7 downto 0);

signal RAM: ram_type := (0 => std_logic_vector(to_unsigned( 12, 8)),
                         1 => std_logic_vector(to_unsigned( 23, 8)),
                         2 => std_logic_vector(to_unsigned( 32, 8)),
                         3 => std_logic_vector(to_unsigned( 44, 8)),
                         4 => std_logic_vector(to_unsigned( 55, 8)),
                         5 => std_logic_vector(to_unsigned( 66, 8)),
                         6 => std_logic_vector(to_unsigned( 77, 8)),
                         7 => std_logic_vector(to_unsigned( 99, 8)),
             others => (others =>'0'));

component project is
port (
      ....
      ...
      );
end component project;


begin
UUT: project
port map (
          ....

          );

p_CLK_GEN : process is
begin
    ....
end process p_CLK_GEN;


MEM : process(clk)
begin
    ....
    ....
end process;


test : process is
begin 
    wait for 50 ns;
    wait for c_CLOCK_PERIOD;
    tb_rst <= '1';
    wait for c_CLOCK_PERIOD;
    tb_rst <= '0';
    wait for c_CLOCK_PERIOD;
    tb_start <= '1';
    wait for c_CLOCK_PERIOD;
    wait until tb_done = '1';
    wait for c_CLOCK_PERIOD;
    tb_start <= '0';
    wait until tb_done = '0';


    assert RAM(20) = std_logic_vector(to_unsigned( 13, 8)) report "failed" severity notice;

    assert false report "passed" severity notice;
end process test;