Question

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fsm is
    Port ( clock : in  STD_LOGIC;
           P : in  STD_LOGIC_VECTOR(4 downto 0);
           reset : in  STD_LOGIC;
           State : out  STRING);
end fsm;

architecture Behavioral of fsm is
TYPE State_type IS (Initial, Starting,Closed,Closing,Stopped,Stopping,Req_sent,Opened,Ack_sent,Ack_rcvd);  -- Define the states
SIGNAL State : State_Type;    -- Create a signal that begin

begin
PROCESS (clock,reset)
BEGIN 
    If (reset = "1") THEN    
    State <= Initial;

    ELSE IF rising_edge(clock) THEN    -- if there is a rising edge 
             -- clock, then do the stuff below

    -- The CASE statement checks the value of the State    
    -- and based on the value and any other control signals, --change s to a new state.

    CASE State IS


        WHEN Initial => 
            IF P="00000" THEN 
                State <= Closed;
            ELSIF P="00010" THEN
                State<=Starting;
            ELSIF P="00011" THEN
                State<=Initial ;
            END IF; 



        WHEN Starting => 
            IF P <="00000" THEN 
                State <= Req_sent;
            ELSIF P <="00010" THEN
                State<=Starting;
            END IF; 

        WHEN Closed => 
            IF P <="00010" THEN 
                State <= Req_sent;
            ELSIF P <="00001" THEN
                State<=Initial;
            ELSIF P <="00100" THEN
                State<=Closed; 
            END IF; 


        WHEN Stopped=> 
            IF P <="00110" THEN 
                State <= Stopped; 
            ELSIF P <="00011" THEN
                State <=Closed ; 
            ELSIF P <="00001" THEN
                State<=Starting;
            ELSIF P <="01101" THEN
                State<=Req_sent;
            ELSIF P <="01100" THEN          
                State<=Ack_sent;
            END IF; 

        WHEN Closing =>
            IF P <="00101" THEN
                State <= Closing;
            ELSIF P <="00001" THEN
                State<=Initial;
            ELSIF P <="01110" THEN
                State<=Closed;
            ELSIF P <="00010" THEN
                State<=Stopping;
            END IF;

        WHEN Req_sent=>
            IF P <="01001" THEN
                State<=Req_sent;
            ELSIF P <="01101" THEN
                State<=Opened;
            ELSIF P <="01100" THEN
                State<=Ack_sent;
            ELSIF P <="10000" THEN
                State<=Ack_rcvd;
            ELSIF P <="10011" THEN
                State<=Stopped;
            ELSIF P <="00001" THEN
                State<=Starting;
            ELSIF P <="00011" THEN
                State<=Closing;
            END IF;

        WHEN Stopping=>
            IF P <="00111" THEN
                State<=Stopping;
            ELSIF   P <="00011" THEN
                State<=Closing;
            ELSIF P <="01110" THEN
                State<=Stopped;
            ELSIF P <="00001" THEN
                State<=Starting;
            END IF;

        WHEN Opened=>
            IF P <="01000" THEN
                State<=Opened;
            ELSIF P <="00001" THEN
                State<=Starting;
            ELSIF P <="00011" THEN
                State<=Closing;
            ELSIF P <="01111" THEN
                State<=Stopping;
            ELSIF P <="01100" THEN
                State<=Ack_sent;
            END IF;

        WHEN Ack_sent=>
            IF P <="01010" THEN
                State<=Ack_sent;
            ELSIF P <="00011" THEN
                State<=Closing;
            ELSIF P <="10000" THEN
                State<=Opened;
            ELSIF P <="10010" THEN
                State<=Red_sent;
            ELSIF P <="00001" THEN
                State<=Starting;
            ELSIF P <="10011" THEN
                State<=Stopped;
            END IF;

        WHEN Ack_rcvd=>
            IF P <="01011" THEN
                State<=Ack_rcvd;
            ELSIF P <="10000" THEN
                State<=Opened;
            ELSIF P <="00011" THEN
                State<=Closing;
            ELSIF P <="10001" THEN
                State<=Req_sent;
            ELSIF P="10011" THEN
                State<=Stopped;
            ELSIF P <="00001" THEN
                State<=Starting;
            END IF;


    END CASE; 
   END IF; 
 END PROCESS;

end Behavioral;

请帮我弄清楚这段代码中的错误。已经尝试了几个小时

错误：HDLC编译器：806 - ＆＃34; C：/。Xilinx / fsm / fsm.vhd＆＃34;第184行：＆＃34; PROCESS＆＃34;。
附近的语法错误

Answer 1

有几个错误。

您的内部信号State是实体信号State
您的重置检查使用"1"，时间应为'1'
您使用Red_sent代替Req_sent

但是导致错误消息的问题是，您使用的是ELSE IF而不是ELSIF。

使用VHDL实现ppp有限状态机

1 个答案: