Question

我有一个无法修改的Verilog程序，它需要16个输入和1个输出。我能够在VHDL中创建包装器，并且如果我从外部提供输入，一切都会按预期工作。

我希望能够在内部修改包装器（pi16）的最后输入，并且我有以下包装器代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity DD_Wrapper is
port(
pi00 : in STD_LOGIC;
pi01 : in STD_LOGIC;
pi02 : in STD_LOGIC;
pi03 : in STD_LOGIC;
pi04 : in STD_LOGIC;
pi05 : in STD_LOGIC;
pi06 : in STD_LOGIC;
pi07 : in STD_LOGIC;
pi08 : in STD_LOGIC;
pi09 : in STD_LOGIC;
pi10 : in STD_LOGIC;
pi11 : in STD_LOGIC;
pi12 : in STD_LOGIC;
pi13 : in STD_LOGIC;
pi14 : in STD_LOGIC;
pi15 : in STD_LOGIC;
--pi16 : in STD_LOGIC;
po0 : out STD_LOGIC

);
end DD_Wrapper;


architecture Behavioral of DD_Wrapper is

component DD
    port (
    pi00 : in STD_LOGIC;
    pi01 : in STD_LOGIC;
    pi02 : in STD_LOGIC;
    pi03 : in STD_LOGIC;
    pi04 : in STD_LOGIC;
    pi05 : in STD_LOGIC;
    pi06 : in STD_LOGIC;
    pi07 : in STD_LOGIC;
    pi08 : in STD_LOGIC;
    pi09 : in STD_LOGIC;
    pi10 : in STD_LOGIC;
    pi11 : in STD_LOGIC;
    pi12 : in STD_LOGIC;
    pi13 : in STD_LOGIC;
    pi14 : in STD_LOGIC;
    pi15 : in STD_LOGIC;
    pi16 : in STD_LOGIC;

    po0 : out STD_LOGIC 
    );
end component;

-- Trying to modify input pi16
signal pi16_new : std_logic := '1';

begin
    DD_x : DD
    port map (
    pi00 => pi00,
    pi01 => pi01,
    pi02 => pi02,
    pi03 => pi03,
    pi04 => pi04,
    pi05 => pi05,
    pi06 => pi06,
    pi07 => pi07,
    pi08 => pi08,
    pi09 => pi09,
    pi10 => pi10,
    pi11 => pi11,
    pi12 => pi12,
    pi13 => pi13,
    pi14 => pi14,
    pi15 => pi15,
    pi16 => pi16_new,

    po0 => po0 
    );

-- Trying to modify input pi16
    process is 
        begin
            pi16_new <= pi16_new xor '1';
            wait for 500 ms;
    end process; 
end Behavioral;

我正在使用Vivado模拟程序，Behavioral Simulation给了我正确的结果，但是如果我运行Post-Synthesis Functional Simulation，则输出po0始终是未知的（{{1} }。我还尝试将代码刷新到FPGA中，输出似乎是随机的。

为什么会这样？我似乎找不到错误。

FPGA：Verilog文件的VHDL包装器

0 个答案: