VHDL中的位移位会产生错误

Question

我试图对std_logic_vector进行位移位，但是无论我尝试什么，我总是会遇到错误。

我尝试使用srl和shift_right，但我认为使用它更安全。它们都不被编译器接受，或者至少我犯了我找不到的语法错误。我还尝试将结果转换为std_logic_vector。

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity EXAMPLE is
    port(
        VOL_LEVEL           : in integer range 1 to 10; -- from AUDIO_VOL
        LED_OUT             : out std_logic_vector(9 downto 0)
    );
end entity EXAMPLE;

architecture BEHAVIOUR of EXAMPLE is

type STATES is (S_SET_VOL);

signal STATE, NEXT_STATE : STATES;

EXAMPLE: process(VOL_LEVEL)
begin
    case STATE is
        when S_SET_VOL =>

        LED_OUT <= ("1111111111") srl (10-VOL_LEVEL) after 2 ns; 
         -- Type error resolving infix expression "srl" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.

        LED_OUT <= shift_right(unsigned("1111111111"), 10-VOL_LEVEL) after 2 ns;
         -- No feasible entries for subprogram "SHIFT_RIGHT".

        LED_OUT <= std_logic_vector(shift_right(unsigned("1111111111"), 10-VOL_LEVEL)) after 2 ns;
         -- Type conversion (to UNSIGNED) cannot have string literal operand.

end process EXAMPLE;

end BEHAVIOUR;