-尝试创建一个由多路复用器选择的输出端口的内存模块。我是一名初学者VHDL编码器，我已经读到它与在多个进程中描述的输出有关，但是我的代码中只有一个进程，因此我对从这里去哪里有些困惑。 133行位于clk的UUT_Outport内部。
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory is
generic(width : positive := 32);
port (
writeEn : in std_logic;
output : out std_logic_vector(WIDTH-1 downto 0);
InPort0_en, InPort1_en : in std_logic:= '0';
Outport_en : in std_logic:= '0';
B_out :in std_logic_vector(31 downto 0):= (others => '0');
switches : in std_logic_vector(9 downto 0);
buttons : in std_logic_vector(1 downto 0):= (others => '0');
rd_data : out std_logic_vector(1 downto 0);
wr_data : in std_logic_vector(31 downto 0):= (others => '0');
clk : in std_logic:= '0';
OutPort : out std_logic_vector(WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(31 downto 0)
);
end memory;
architecture BHV of memory is
signal ram_out : std_logic_vector (31 downto 0);
signal InPort0out : std_logic_vector(31 downto 0);
signal InPort1out : std_logic_vector(31 downto 0);
signal mux_sel : std_logic_vector(1 downto 0);
component ram_256 is
port
(
address : in std_logic_vector (31 downto 0);
clock : in std_logic;
data : in std_logic_vector (31 downto 0);
wren : in std_logic ;
q : out std_logic_vector (31 downto 0)
);
end component;
component reg32 is
port
(
rst: in std_logic := '0';
clk: in std_logic;
en: in std_logic := '0';
ld: in std_logic := '0';
d: in std_logic_vector(31 downto 0) := (others => '0');
q: buffer std_logic_vector(31 downto 0)
);
end component;
component mux4x1 is
generic (
width : natural := 32);
port (
in1 : in std_logic_vector(width-1 downto 0);
in2 : in std_logic_vector(width-1 downto 0);
in3 : in std_logic_vector(width-1 downto 0);
in4 : in std_logic_vector(width-1 downto 0);
sel : in std_logic_vector(1 downto 0);
output : out std_logic_vector(width-1 downto 0)
);
end component;
begin
process(switches,buttons,ADDRESS,writeEn,InPort0out,InPort1out,mux_sel)
begin
case writeEn is
when '0' =>
if (ADDRESS = x"0000FFF8") and (switches(9) = '0') then
Inport0out <= std_logic_vector(resize(unsigned(switches(9 downto 0)), ADDRESS'length));
mux_sel <= "00";
elsif (ADDRESS = x"0000FFFC") and (switches(9) = '1')then
Inport1out <= std_logic_vector(resize(unsigned(switches(9 downto 0)), ADDRESS'length));
mux_sel <= "01";
elsif ((ADDRESS >= x"00000000") and (ADDRESS <= x"00000100")) then
mux_sel <= "10";
else
mux_sel <= "11";
end if;
when '1' =>
if (ADDRESS <= x"0000FFFC") then
outport <= B_out;
end if;
end case;
end process;
UUT_inport0 : entity work.reg32
port map (
clk => clk,
ld => '1',
en => buttons(1),
d => std_logic_vector(resize(unsigned(switches(9 downto 0)), ADDRESS'length)),
q => InPort0out
);
UUT_inport1 : entity work.reg32
port map (
clk => clk,
ld => '1',
en => buttons(1),
d => std_logic_vector(resize(unsigned(switches(9 downto 0)), ADDRESS'length)),
q => InPort1out
);
UUT_Outport : entity work.reg32
port map (
clk => clk,
ld => '1',
en => Outport_en,
d => B_out,
q => Outport
);
UUT : ram_256
port map(
address => ADDRESS(9 downto 2),
clock => clk,
data => B_out,
wren => writeEn,
q => ram_out
);
MEM_MUX : entity work.mux4x1
port map (
in1 => InPort0out,
in2 => InPort1out,
in3 => ram_out,
in4 => x"00000000",
sel => mux_sel,
output => Outport
);
end BHV;