对32位寄存器进行8位写操作

时间:2019-04-07 17:14:54

标签: c memory-management arm cpu-registers

我正在尝试在Samd21 MCU上读取给定clock source的{​​{1}}值。

数据表说,如果我想读取generic clock generator寄存器(包含时钟源值),则需要“进行8位写入”,然后再读取该寄存器。鉴于寄存器是32位的,我该怎么办?

恐怕通过执行以下操作,实际上是在更改GENCTRL的配置:

generic clock generator X

请记住,GCLK->GENCTRL.reg = GCLK->GENCTRL.reg & 0xFFFFFFF0 | 0x0000000X 的低8位是为通用时钟发生器的ID保留的。

黄色是datasheet的一部分,其中包含读取GENCTRL寄存器的说明。

Datasheet

1 个答案:

答案 0 :(得分:1)

The ARM registers are 32 bit. The peripheral registers (in general) will be arranged at 4 byte offsets, but will not always implement all 32 bits that this implies.

This is most obvious when the upper bits of a peripheral register are 'read as zero, write ignored'. You might occasionally see a newer or more featured version of the peripheral where some of these unused bits become used in the future.

Depending on exactly how a specific peripheral is connected to the core it is generally possible to perform byte, half-word or word accesses to any region of memory. Provided this is supported, only the relevant bytes will be updated. Where there is a restriction (for example a 32 bit APB bus where only byte access is supported), this should be clearly identified in the documentation. With a AA64 processor, it is even possible to write two registers at once!

Do note that the peripheral 'knows' the access size (at least the information is present on the internal bus), so it is possible to specify different behaviour for a byte access as a word (even if this is the sort of confusing behaviour that is best avoided). To generalise, any memory mapped peripheral is more of an observer of the bus than a true implementation of memory - the designer is free to play tricks with the full address/data/control bus bit combinations, and implement bitmasks, read/modify/write, access locks, magic values, etc.