波形中的计数器值与代码中的条件不匹配

Question

在下面的代码中，当计数器大于4时，我的状态应该从2更改为3，但是在我的波形中，状态应该一直变为9，而当计数器应该大于2时，才开始从1更改为2。 3.

总输出是一个16位输出寄存器，而number_one是我给用户的四位输入。

module project7(clock , reset , number_one , total_output , present , next , counter );
input clock , reset ;
input [3:0] number_one ; // 4 bit input from the user
output reg[16:1] total_output = 0 ; 

output reg[3:0] present = 0 , next = 0 ;
output reg [3:0]counter = 0;
//output reg [3:0] number1 , number2 , number3 , number4 ;

parameter s1 = 4'd1 , s2 = 4'd2 , s3 = 4'd3 , s4 = 4'd4;
always@(*)
begin 
case(present)
s1 :begin  if (number_one == 4'd0 && counter == 0) next = s1 ; 

else if ( number_one <= 4'd9 && counter <= 4'b0100  ) next = s2 ;
else next = s3 ; end 

s2 : next = s1 ;
s3 : next = s3 ;
default : next = s1 ;
endcase
end 

always @ (posedge clock or posedge reset)
   if(reset) present <=s1;
   else 

   present<=next;



always@(posedge clock)
begin 
case(present)
s1 :
 begin 
 counter <= counter +1 ;
 total_output <= {number_one , total_output[16:5]};

end


s2 : begin 
counter <= counter +1 ;
total_output <=  {number_one , total_output[16:5]};

 end 

s3 : begin
total_output <= total_output ;


end 
endcase
end 
endmodule

这是我的测试台代码。

module simulation();

reg clock ; 
reg reset ;
reg [3:0] number_one ; 
wire [16:1] total_output ; 
wire [3:0] present , next;
wire [3:0] counter  ; 
wire [3:0] number1 , number2 , number3 , number4;
project7 uut (clock , reset , number_one , total_output ,  present , next , counter , number1 , number2 , number3 , number4  );

initial 
 clock =1 ;
 always
 #50 clock = ~clock;

initial begin

reset = 1'b1;#100;
reset = 1'b0;#100;
end

initial begin 
number_one[3:0]  = 4'd3;#100;
number_one[3:0]  = 4'd4;#100;
number_one[3:0]  = 4'd2;#100;
number_one[3:0]  = 4'd1;#100;
number_one[3:0]  = 4'd5;#100;


end 
endmodule