Question

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity keygeneration is
    Port ( key : in  STD_LOGIC_VECTOR (127 downto 0);
           rc : in  STD_LOGIC_VECTOR (3 downto 0);
           keyout : out  STD_LOGIC_VECTOR (127 downto 0));
end keygeneration;

architecture Behavioral of keygeneration is

component sbox is
     port(a: in std_logic_vector(7 downto 0);
          y: out std_logic_vector(7 downto 0));
end component;
component RCON is
 Port ( rc : in  STD_LOGIC_VECTOR (3 downto 0);
            rout : out  STD_LOGIC_VECTOR (31 downto 0));
end component;
signal w0,w1,w2,w3,tem: STD_LOGIC_VECTOR (31 downto 0);
signal rout1: STD_LOGIC_VECTOR (31 downto 0);

begin
-- 52nd line below
w0<=key[127 downto 96];
w1<=key[95 downto 64];
w2<=key[63 downto 32];
w3<=key[31 downto 0];

t1: sbox port map(w3[23 downto 16],tem[31 downto 0]);
t2: sbox port map(w3[15 downto 8],tem[23 downto 16]);
t3: sbox port map(w3[7 downto 0],tem[15 downto 8]);
t4: sbox port map(w3[31 downto 24],tem[7 downto 0]);

r1: RCON port map(rc[3 downto 0],rout1[31 downto 0]);

keyout[127 downto 96]<=w0^tem^rout1;
keyout[95 downto 64]<=w0^tem^rout1^w1;
keyout[63 downto 32]<=w0^tem^rout1^w1^w2;
keyout[31 downto 0]<=w0^tem^rout1^w1^w2^w3;

end Behavioral;

发现的错误是

ERROR：HDLParsers：164-“ D：/Files/newpro/keygeneration.vhd”第52行。解析错误，意外的INTEGER_LITERAL，预期返回或 IDENTIFIER或RSQBRACK。

我已经在代码中显示了第52行。对于第52行的所有赋值语句，我都有相同的错误。请帮助。预先感谢

Answer 1

2个错误：

VHDL不会将[]用于索引数组（尽管它们用于签名）。使用()来索引数组。

VHDL中没有^运算符。请改用xor。

Answer 2

你不是这个意思：

w0<=key[127 downto 96];

您的意思是：

w0<=key(127 downto 96);

我已经用VHDL为我的项目编写了代码，但是在使用signal

2 个答案: