Question

我编写了以下VHDL代码，它是快速加法器的组件。快速加法器由一个8by8寄存器组成，该寄存器连接到加法器，其代码如下。如何消除inout Read_Adress的使用。我想让Read_Adress出来std_logic_vector而不是inout？

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

Entity Adder is
port(
        Clock_50_MHZ :in std_logic;
        En :in std_logic;
        Data_Registerfile : in std_logic_vector(7 downto 0);
        Read_Address: inout std_logic_vector(2 downto 0) := "000";
            Output : out std_logic_vector(11 downto 0)
 );
 end Adder;

 Architecture arch of Adder is
 Signal result : unsigned (11 downto 0):="000000000000";
 Signal regData: std_logic_vector(7 downto 0);

 Begin
 regData <= Data_Registerfile;
 Process(Clock_50_MHZ)
Begin
if rising_edge(Clock_50_MHZ)  then
    if (En = '1') then
        if(Read_Address = "000") then
            result <= "000000000000" + unsigned(regData);
            Read_Address <= Read_Address + 1;
        elsif(Read_Address = "111") then
            Output <= std_logic_vector( result + unsigned(regData) );
            Read_Address <= "000";
        else
            result <= result + unsigned(regData);
            Read_Address <= Read_Address + 1;
        end if;
    end if;
end if;
 End Process;
end arch;

Answer 1

这在VHDL中是一个经典的不便：你不能使用你的out端口信号（如果你习惯了Verilog，你经常会发现自己想做的事情这一点）。

我所知道的最好的方法是创建一个额外的虚拟信号：

signal Read_Address_tmp : std_logic_vector(2 downto 0) := "000";

用那个计算：

     Process(Clock_50_MHZ)
 Begin
 if rising_edge(Clock_50_MHZ)  then
     if (En = '1') then
         if(Read_Address_tmp = "000") then
             result <= "000000000000" + unsigned(regData);
             Read_Address_tmp <= Read_Address_tmp + 1;
         elsif(Read_Address_tmp = "111") then
             Output <= std_logic_vector( result + unsigned(regData) );
             Read_Address_tmp <= "000";
         else
             result <= result + unsigned(regData);
             Read_Address_tmp <= Read_Address_tmp + 1;
         end if;
     end if;
 end if;
  End Process;

然后将其链接到您的输出：

Read_Address <= Read_Address_tmp;

Answer 2

欧文的答案是历史上通常的方式。

“新”VHDL 2008允许现在读取输出模式端口。如果您的工具不支持它，请记录供应商的错误。请参阅本页底部的“VHDL 2008 - 只是新内容”

http://books.google.co.uk/books?id=ETxLguPMEY0C&pg=PA163&lpg=PA163#v=onepage&q&f=false

我如何消除我的vhdl Adder的inout信号？

2 个答案: