我最近开始遇到ISE问题。 ISE现在拒绝为我的项目生成位流，而没有控制台错误。经过进一步调查，我在bitgen报告中发现了此错误：
ERROR::102 - The design 'core.ncd' is missing any BMM information for
given BRAM data files. BRAMs can't be initialized with the given data without
BMM information. Either BMM information must be given to NGDBuild with a '-bm'
option, or embedded BMM information must be included in the source HDL.
我不知道这意味着什么，而且几乎没有任何有用的信息。我已经花了数小时试图解决这个问题。由于它似乎与内存初始化有关，因此我尝试删除$ readmemh和$ readmemb调用，但这并不能解决问题。创建一个新项目并导入代码也无法修复它。我有另一个项目会生成比特流，但是我没有做任何不同的事情。
这可能有关系，但可能与ISim有关。开始仿真后，出现错误“错误：数据文件IDecoder.mem中指定的单词过多”。尝试访问任何较高的操作码会导致控制总线上的值未定义。我也不确定为什么会这样，因为微程序分配的字数是IDecoder.mem中定义的两倍。
这是一个不完整的项目，部分代码尚未完成。
core.v：
`timescale 1ns / 1ps
module core(
input clk, rst,
output reg [7:0] leds
);
reg [15:0] dstack [0:63];
reg [15:0] rstack [0:63];
reg [6:0] dstack_ptr = 0, rstack_ptr = 0;
reg [15:0] ins_ptr = 0;
reg [7:0] memory [0:16383];
reg [31:0] microprogram [0:255];
reg [31:0] controlword = 0;
reg [15:0] buffers [0:3];
wire [1:0] buffsel;
assign buffsel = controlword[13:12];
wire [1:0] jumpsel;
assign jumpsel = controlword[16:15];
wire [4:0] aluop;
assign aluop = controlword[21:17];
reg [2:0] mi_counter = 3'd0;
reg pause = 1'd0;
reg halt = 1'd0;
reg [7:0] err = 8'd0;
reg [7:0] opcode = 8'd0;
initial begin
$readmemh("IDecoder.mem", microprogram);
$readmemb("memory.mem", memory);
buffers[0] = 0;
buffers[1] = 0;
buffers[2] = 0;
buffers[3] = 0;
end
always @(negedge clk) begin
if (rst) begin
controlword <= 32'd0;
end else begin
if (!halt && !pause) begin
controlword <= microprogram[{((opcode > 8'd127) ? 8'd128 : opcode), mi_counter}]; //Ignore opcodes > 128
end
end
end
always @(posedge clk) begin
if (rst) begin
opcode <= 0;
ins_ptr <= 0;
dstack_ptr <= 0;
rstack_ptr <= 0;
pause <= 0;
halt <= 0;
mi_counter <= 0;
buffers[0] <= 0;
buffers[1] <= 0;
buffers[2] <= 0;
buffers[3] <= 0;
err <= 0;
leds <= 0;
end else begin
if (controlword[0]) begin //HALT
halt <= 1;
leds <= err;
end
if (controlword[1]) pause <= 1; //PAUSE
if (controlword[2]) mi_counter <= 0; else if (!pause && !halt) mi_counter <= mi_counter + 1; //RST MCC
if (controlword[3]) opcode <= memory[ins_ptr]; //FETCH OPCODE
if (controlword[4]) ins_ptr <= ins_ptr + 1; //IP INC
if (controlword[5]) buffers[buffsel] <= {buffers[buffsel][15:8], memory[ins_ptr]}; //BUFFER FETCH LSB
if (controlword[6]) buffers[buffsel] <= {memory[ins_ptr], buffers[buffsel][7:0]}; //BUFFER FETCH MSB
if (controlword[7]) begin //BUFFER CLEAR
buffers[0] <= 0;
buffers[1] <= 0;
buffers[2] <= 0;
buffers[3] <= 0;
end
if (controlword[8]) begin //BUFFER PUSHD
if (dstack_ptr > 63) begin
halt <= 1;
err <= 1; //DSTACK OVERFLOW
end else begin
dstack[dstack_ptr] <= buffers[buffsel];
dstack_ptr <= dstack_ptr + 1;
end
end
if (controlword[9]) begin //BUFFER PUSHR
if (rstack_ptr > 63) begin
halt <= 1;
err <= 2; //RSTACK OVERFLOW
end else begin
rstack[rstack_ptr] <= buffers[buffsel];
rstack_ptr <= rstack_ptr + 1;
end
end
if (controlword[10]) begin //BUFFER POPD
if (dstack_ptr < 1) begin
halt <= 1;
err <= 3; //DSTACK UNDERFLOW
end else begin
buffers[buffsel] <= dstack[dstack_ptr-1];
dstack_ptr <= dstack_ptr - 1;
end
end
if (controlword[11]) begin //BUFFER POPR
if (rstack_ptr < 1) begin
halt <= 1;
err <= 4; //RSTACK UNDERFLOW
end else begin
buffers[buffsel] <= rstack[rstack_ptr-1];
rstack_ptr <= rstack_ptr - 1;
end
end
//12 & 13 are the buffer select
if (controlword[14]) begin //JUMP
if (buffers[0] > 16383) begin //Invalid jump target
halt <= 1;
err <= 5; //INVALID JUMP ADDRESS
end else begin
case(jumpsel)
3'd0: ins_ptr <= buffers[0]; //Unconditional jump
3'd1: begin //Jump if zero
if (buffers[1] == 0) ins_ptr <= buffers[0];
end
3'd2: begin //Jump if not zero
if (buffers[1] != 0) ins_ptr <= buffers[0];
end
default: begin //Should never happen
halt <= 1;
err <= 255; //UNKNOWN ERROR
end
endcase
end
end
//15 - 16 are the jump select
//17 - 21 are the ALU opcode
if (controlword[22]) begin //ALU
case (aluop)
0: buffers[0] <= buffers[0] + 16'd1; //INC
1: buffers[0] <= buffers[0] - 16'd1; //DEC
2: buffers[0] <= buffers[0] + buffers[1]; //ADD
3: buffers[0] <= buffers[0] - buffers[1]; //SUB
4: buffers[0] <= buffers[0] * buffers[1]; //MUL
5: buffers[0] <= buffers[0] << buffers[1]; //LSHIFT
6: buffers[0] <= buffers[0] >> buffers[1]; //RSHIFT
7: buffers[0] <= ~buffers[0]; //NOT
8: buffers[0] <= buffers[0] & buffers[1]; //AND
9: buffers[0] <= buffers[0] | buffers[1]; //OR
10: buffers[0] <= buffers[0] ^ buffers[1]; //XOR
//COMPARISON OPERATORS
24: buffers[0] <= (buffers[0] <= buffers[1]) ? 16'd1 : 16'd0; //(A LEQ B)
25: buffers[0] <= (buffers[0] >= buffers[1]) ? 16'd1 : 16'd0; //(A GEQ B)
26: buffers[0] <= (buffers[0] < buffers[1]) ? 16'd1 : 16'd0; //(A LT B)
27: buffers[0] <= (buffers[0] > buffers[1]) ? 16'd1 : 16'd0; //(A GT B)
28: buffers[0] <= (buffers[0] != buffers[1]) ? 16'd1 : 16'd0; //(A NEQ B)
29: buffers[0] <= (buffers[0] == buffers[1]) ? 16'd1 : 16'd0; //(A EQ B)
30: buffers[0] <= (buffers[0] != 16'd0) ? 16'd1 : 16'd0; //(A NEQ 0)
31: buffers[0] <= (buffers[0] == 16'd0) ? 16'd1 : 16'd0; //(A EQ 0)
default: buffers[0] <= 16'b0;
endcase
end
end
end
endmodule
memory.mem：
00000010 00000000 //LIT1 0
00011010 //EQ 0
00000001 //HALT
IDecoder.mem：
//OPCODE 0
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 1
00000098
00000001
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 2
00000098
00000030
00000100
00000004
00000004
00000004
00000004
00000004
//OPCODE 3
00000098
00000050
00000030
00000100
00000004
00000004
00000004
00000004
//OPCODE 4
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 5
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 6
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 7
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 8
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 9
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 10
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 11
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 12
00000098
00000050
00000030
00004000
00000004
00000004
00000004
00000004
//OPCODE 13
00000098
00000050
00000030
00001400
0000c000
00000004
00000004
00000004
//OPCODE 14
00000098
00000050
00000030
00001400
00014000
00000004
00000004
00000004
//OPCODE 15
00000098
00000400
00400000
00000100
00000004
00000004
00000004
00000004
//OPCODE 16
00000098
00000400
00420000
00000100
00000004
00000004
00000004
00000004
//OPCODE 17
00000098
00000400
00001400
00440000
00000100
00000004
00000004
00000004
//OPCODE 18
00000098
00000400
00001400
00460000
00000100
00000004
00000004
00000004
//OPCODE 19
00000098
00000400
00001400
00480000
00000100
00000004
00000004
00000004
//OPCODE 20
00000098
00000400
00001400
004a0000
00000100
00000004
00000004
00000004
//OPCODE 21
00000098
00000400
00001400
004c0000
00000100
00000004
00000004
00000004
//OPCODE 22
00000098
00000400
004e0000
00000100
00000004
00000004
00000004
00000004
//OPCODE 23
00000098
00000400
00001400
00500000
00000100
00000004
00000004
00000004
//OPCODE 24
00000098
00000400
00001400
00520000
00000100
00000004
00000004
00000004
//OPCODE 25
00000098
00000400
00001400
00520000
00000100
00000004
00000004
00000004
//OPCODE 26
00000098
00000400
007e0000
00000100
00000004
00000004
00000004
00000004
//OPCODE 27
00000098
00000400
007c0000
00000100
00000004
00000004
00000004
00000004
//OPCODE 28
00000098
00000400
00001400
007a0000
00000100
00000004
00000004
00000004
//OPCODE 29
00000098
00000400
00001400
00780000
00000100
00000004
00000004
00000004
//OPCODE 30
00000098
00000400
00001400
00760000
00000100
00000004
00000004
00000004
//OPCODE 31
00000098
00000400
00001400
00740000
00000100
00000004
00000004
00000004
//OPCODE 32
00000098
00000400
00001400
00720000
00000100
00000004
00000004
00000004
//OPCODE 33
00000098
00000400
00001400
00700000
00000100
00000004
00000004
00000004
//OPCODE 34
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 35
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 36
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 37
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 38
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 39
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 40
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 41
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 42
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 43
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 44
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 45
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 46
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 47
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 48
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 49
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 50
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 51
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 52
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 53
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 54
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 55
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 56
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 57
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 58
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 59
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 60
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 61
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 62
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 63
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 64
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 65
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 66
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 67
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 68
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 69
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 70
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 71
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 72
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 73
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 74
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 75
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 76
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 77
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 78
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 79
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 80
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 81
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 82
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 83
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 84
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 85
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 86
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 87
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 88
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 89
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 90
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 91
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 92
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 93
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 94
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 95
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 96
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 97
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 98
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 99
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 100
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 101
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 102
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 103
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 104
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 105
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 106
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 107
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 108
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 109
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 110
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 111
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 112
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 113
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 114
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 115
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 116
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 117
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 118
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 119
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 120
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 121
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 122
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 123
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 124
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 125
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 126
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 127
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
//OPCODE 128
00000098
00000004
00000004
00000004
00000004
00000004
00000004
00000004
coretest.v：
时间刻度1ns / 1ps
module coretest;
// Inputs
reg clk;
reg rst;
// Outputs
wire [7:0] leds;
integer i=0;
// Instantiate the Unit Under Test (UUT)
core uut (
.clk(clk),
.rst(rst),
.leds(leds)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
while (i < 10000) begin
clk = !clk;
#5;
end
end
endmodule