计算输入信号中的“ 01”序列

时间:2019-02-07 22:06:22

标签: vhdl

我的目标是计算import ray ray.init() # Define inner calculation as a remote function. @ray.remote def inner_calculation(asset, trader): return trader # Define outer calculation to be executed as a remote function. @ray.remote(num_return_vals = 2) def outer_calculation(asset): return asset, [inner_calculation.remote(asset, trader) for trader in range(5)] # Helper to convert a nested list of object ids to a nested list of corresponding objects. def ids_to_vals(ids): if isinstance(ids, ray.ObjectID): ids = ray.get(ids) if isinstance(ids, ray.ObjectID): return ids_to_vals(ids) if isinstance(ids, list): results = [] for id in ids: results.append(ids_to_vals(id)) return results return ids outer_result_ids = [] inner_result_ids = [] for asset in range(10): outer_result_id, inner_result_id = outer_calculation.remote(asset) outer_result_ids.append(outer_result_id) inner_result_ids.append(inner_result_id) outer_results = ids_to_vals(outer_result_ids) inner_results = ids_to_vals(inner_result_ids) 数组中“ 01”序列的数量。 我尝试了以下代码,但是它没有像我想象的那样起作用。

iaI

1 个答案:

答案 0 :(得分:1)

vhdl中的信号和变量之间存在显着差异。尽管变量立即获取赋值,但是使用顺序代码(如过程)中的信号来创建触发器,其固有地不会立即获取赋值。您应该在此处使用变量来实现所需的功能。

entity prob35 is
port (
    iaI : in   std_logic_vector (11 downto 0);
    oaO : out  std_logic_vector (2 downto 0)
);
end prob35;

architecture Behavioral of prob35 is
begin
process(iaI)
    variable counter : unsigned(2 downto 0) := "000";
begin
    counter := "000";
    for i in 1 to 11 loop
        if (iaI(i-1)='1' and iaI(i)='0') then
            counter := counter + 1;
        end if;
    end loop;
    oaO <= std_logic_vector(counter);
end process;

end Behavioral;