我试图生成可变长度的路由器网格（每个路由器是一个模块），可以使用两个参数来指定该网格。虽然模块的I / O端口数量是固定的，但连接是在内部生成的，并已适当地连接到I / O。我已经成功生成了所有端口，但是无法生成路由器。 Verilog编译器抛出错误：
条件表达式无法解析为常量
错误与路由器的生成有关。两个for循环中的表达式无法求值，因此是条件表达式。我试图把所有东西都放在一块，但没有运气。
代码如下：
`timescale 1ns / 1ps
`define n ((i-1)*NUMBER_OF_ROUTER_COLS + j)
module top_n_router #(parameter NUMBER_OF_ROUTER_ROWS = 2, NUMBER_OF_ROUTER_COLS = 2)(
input clk, clr,
input [7:0] current_address_r1, current_address_r2, current_address_r3, current_address_r4,
input [31:0] data_in_core_r1, data_in_core_r2, data_in_core_r3, data_in_core_r4,
input full_in_core_vc1_r1, full_in_core_vc2_r1, full_in_core_vc3_r1, full_in_core_vc4_r1,
input full_in_core_vc1_r2, full_in_core_vc2_r2, full_in_core_vc3_r2, full_in_core_vc4_r2,
input full_in_core_vc1_r3, full_in_core_vc2_r3, full_in_core_vc3_r3, full_in_core_vc4_r3,
input full_in_core_vc1_r4, full_in_core_vc2_r4, full_in_core_vc3_r4, full_in_core_vc4_r4,
output reset,
output [31:0] data_out_core_r1, data_out_core_r2, data_out_core_r3, data_out_core_r4,
output full_out_core_vc1_r1, full_out_core_vc2_r1, full_out_core_vc3_r1, full_out_core_vc4_r1,
output full_out_core_vc1_r2, full_out_core_vc2_r2, full_out_core_vc3_r2, full_out_core_vc4_r2,
output full_out_core_vc1_r3, full_out_core_vc2_r3, full_out_core_vc3_r3, full_out_core_vc4_r3,
output full_out_core_vc1_r4, full_out_core_vc2_r4, full_out_core_vc3_r4, full_out_core_vc4_r4
);
localparam NUMBER_OF_ROUTERS = NUMBER_OF_ROUTER_ROWS * NUMBER_OF_ROUTER_COLS;
wire gnd;
wire vdd;
assign gnd=0;
assign vdd=1;
genvar i,j,k,n;
generate
for(i=1; i<=NUMBER_OF_ROUTERS; i=i+1) // input [31:0] data_in_core_r1; to replace such ports
begin : r_dinc
wire [31:0]data_in_core;
end
for(i=1; i<=NUMBER_OF_ROUTERS; i=i+1) // output [31:0] data_out_core_r1; to replace such ports
begin : r_doutc
wire [31:0]data_out_core;
end
for(i=1; i<=NUMBER_OF_ROUTERS; i=i+1) // input [7:0] current_address_r1; to replace such ports
begin : r_addr
wire [31:0]router_addr;
end
for(i=1; i<=NUMBER_OF_ROUTERS; i=i+1) // wire data_out_link3_r1; to replace such ports
begin : r_dout
for(j=1; j<=4; j=j+1)
begin : link
wire [31:0]data_out_r_link;
end
end
for(i=1; i<=NUMBER_OF_ROUTERS; i=i+1) // input full_in_core_vc1_r1; to replace such ports
begin : r_full_i
for(j=1; j<=4; j=j+1)
begin : vc
wire [31:0] full_in_r_vc = 32'd0;
end
end
for(i=1; i<=NUMBER_OF_ROUTERS; i=i+1) // output full_out_core_vc1_r4; to replace such ports
begin : r_full_oc
for(j=1; j<=4; j=j+1)
begin : vc
wire [31:0] full_o_r_vc ;
end
end
for(i=1; i<=NUMBER_OF_ROUTERS; i=i+1) // wire full_out_link1_vc1_r1; to replace such ports
begin : r_full_ol
for(j=1; j<=4; j=j+1)
begin : vc
for(k=0; k<=4; k=k+1)
begin : link
wire [31:0] full_o_r_vc_l;
end
end
end
endgenerate
// Rn = (i-1)*NUMBER_OF_COLS + j ie, numbering of nth router is given by this relation
generate
for(i=1; i<=NUMBER_OF_ROUTER_ROWS; i=i+1)
begin : r_row
if (i==1)
begin
for(j=1; j<=NUMBER_OF_ROUTER_COLS; j=j+1)
begin : r_col
if (j==1)
begin
//instantiate here for top-left corner
end
else if (j == NUMBER_OF_ROUTER_COLS)
begin
//instantiate here for top-right corner
end
else
begin
//instantiate here for upper-most edge
end
end
end
else if (i == NUMBER_OF_ROUTER_ROWS)
begin
begin
for(j=1; j<=NUMBER_OF_ROUTER_COLS; j=j+1)
begin : r_col
if (j==1)
begin
//instantiate here for bottom-left corner
end
else if (j == NUMBER_OF_ROUTER_COLS)
begin
//instantiate here for bottom-right corner
end
else
begin
//instantiate here for lower-most edge
end
end
end
end
else
begin
begin
for(j=1; j<=NUMBER_OF_ROUTER_COLS; j=j+1)
begin : r_col
if (j==1)
begin
//instantiate here for leftmost edge routers
end
else if (j == NUMBER_OF_ROUTER_COLS)
begin
//instantiate here for rightmost edge routers
end
else
begin
//instantiate here for central routers
end
end
end
end
end
endgenerate
endmodule
我正在使用Vivado 2018.1编写此代码。它不会抱怨任何语法错误，但是会在仿真时抛出错误。
任何帮助将不胜感激。谢谢
答案 0 :(得分：0)
我发现了问题所在。显然，该宏无法正常工作（不知道为什么），并且文本“ n”没有被替换。因此，由于符号未定义，因此无法评估for循环中的表达式。只需将n的所有实例替换为((i-1)*NUMBER_OF_ROUTER_COLS + j)，它就可以像魅力一样工作。
还是，有人可以解释为什么宏不能正常工作吗？
编辑： 感谢@Oldfart。引起问题的原因是“ +”周围的空格。