Question

最近我已经为Linux ubuntu下载了[Symphony eda sonata IDE]（http://symphonyeda.com）。

遵循所有安装指南后，我通过ieee库运行了一个vhdl程序。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity full_adder_vhdl_code is
 Port ( A : in STD_LOGIC;
 B : in STD_LOGIC;
 Cin : in STD_LOGIC;
 S : out STD_LOGIC;
 Cout : out STD_LOGIC);
end full_adder_vhdl_code;

architecture gate_level of full_adder_vhdl_code isbegin
     S <= A XOR B XOR Cin ;
     Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;
end gate_level;

我得到了错误：

VHDL0004: ../test1/full_adder.vhdl: (line 2): Invalid design unit 'std_logic_1164' for library 'ieee'
Error: CSVHDL0002: ../test1/full_adder.vhdl: (line 2): syntax error, unexpected '.', expecting LIBRARY_NAME or PACKAGE_NAME
Error: CSVHDL0152: ../test1/full_adder.vhdl: (line 5): Bad resolution function/type 'std_logic'. It is not a function/type
Error: CSVHDL0002: ../test1/full_adder.vhdl: (line 5): syntax error, unexpected ';', expecting TYPE_NAME or LIBRARY_NAME or PACKAGE_NAME
Error: CSVHDL0002: ../test1/full_adder.vhdl: (line 6): syntax error, unexpected IDENTIFIER
Error: CSVHDL0002: ../test1/full_adder.vhdl: (line 7): syntax error, unexpected IDENTIFIER
Error: CSVHDL0002: ../test1/full_adder.vhdl: (line 8): syntax error, unexpected IDENTIFIER
Error: CSVHDL0002: ../test1/full_adder.vhdl: (line 9): syntax error, unexpected IDENTIFIER
Error: CSVHDL0002: ../test1/full_adder.vhdl: (line 10): syntax error, unexpected END

怎么了？

库ieee的无效设计单元std_logic_1164

0 个答案: