Question

我有以下代码

    use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

entity LUT is
    Port ( LUTin : in STD_LOGIC_VECTOR (15 downto 0);
           LUTout : out STD_LOGIC_VECTOR (15 downto 0));
end LUT;

architecture Behavioral of LUT is
signal fullout : std_logic_vector(15 downto 0);
signal tophalf : std_logic_vector(7 downto 0);
signal secondnibble, firstnibble : std_logic_vector(3 downto 0); --break the LSH into 2 nibbles

begin
 tophalf(7 downto 0) <= LUTin(15 downto 8);
 secondnibble(3 downto 0) <= LUTin(7 downto 4);
firstnibble(3 downto 0) <= LUTin(3 downto 0);

 fullout(15 downto 8) <= tophalf(7 downto 0);
--fullout(7 downto 4) <= "0001"; 
fullout(3 downto 0) <= firstnibble(3 downto 0);
p1: process
begin
   case secondnibble is
    when "0000" => --0 Sbox1
       fullout(7 downto 4) <= "0001";
    when others => 
    end case;
    end process;
end Behavioral;

我可以将case语句从p1：process注释到结束过程，并在fullout（7到4）中注释<=“ 0001”;并将0001放入7到4位的全位。我想做的是当LUTin（7 downto 4）<=“ 0000”;时给它0001。所以我需要放置case语句和上面的p1：process。但这意味着将fullout（7降至4）保留为'U'。当它不在case语句中并在case语句中保留为U时，它如何工作？对于第二小节的整个范围，我将做同样的事情。这只是一个简化的案例，所以我可以弄清楚该怎么做

Answer 1

是的。请在架构的“开始”关键字之前初始化完整值，

architecture Behavioral of LUT is
signal fullout : std_logic_vector(15 downto 0) := (others => '0');

这将消除歧义，从而杀死U状态。请记住，始终初始化所有输出，以减轻合成器和模拟器端的歧义。

STD_LOGIC_VECTOR切片并使用case语句再次构建它问题？

1 个答案: