Question

我正在创建VHDL中具有可变位输入的处理元素。我尝试使用generate语句来实例化处理元素的更多组件，并且需要输入为std_logic_vectors，因此可以对其进行参数化，但在尝试合成时会出错。请帮助说明为什么我收到合成错误以及可以采取哪些措施来解决错误。

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package logic_array_type is
constant number_of_PE: integer := 16; -- number of processing elements   
constant    data_width: integer := 8; -- size of datapath, can be changed. 
type vector_array is array (natural range <>) of std_logic_vector(data_width-1 downto 0);--to allow use of signal as CurBlk(i) to connect to the ith generated instanciation of entity/component.
type vector_array2 is array (natural range <>) of std_logic_vector(data_width downto 0);

end package logic_array_type;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.logic_array_type.all;


entity MEengine is
    Generic( 
           number_of_PE: integer := 16; -- number of processing elements   
              data_width: integer := 8; -- size of data_width, can be changed.   
              w: integer := 8); -- w value(size of datapath) can be changed. 

    Port ( reset : in  STD_LOGIC;------ To be indexed in future instantiations
           clk : in  STD_LOGIC;
           sel : in  STD_LOGIC;
           mv : out  STD_LOGIC_VECTOR (w-1 downto 0));
end MEengine;

architecture Behavioral of MEengine is

        component ProEle is
             Generic(w: integer := 8); -- w value can be changed
                Port ( CurBlk : in  STD_LOGIC_VECTOR (w-1 downto 0);
                  RefBlk1 : in  STD_LOGIC_VECTOR (w-1 downto 0);
                  RefBlk2 : in  STD_LOGIC_VECTOR (w-1 downto 0);
                  Sad : out  STD_LOGIC_VECTOR (w downto 0);
                  SEL : in  STD_LOGIC;
                  clk : in  STD_LOGIC;
                  reset : in  STD_LOGIC;
                  lat_en : in  STD_LOGIC;                    -------------- future control for delay latches
                  Dlat : out  STD_LOGIC_VECTOR (w-1 downto 0));
            end component ProEle;



---component specification--

for all : ProEle use entity work.ProEle(behavioral);



----internal signals-------

            signal CurBlk : vector_array(data_width-1 downto 0);
            signal RefBlk1 :vector_array (data_width-1 downto 0);
            signal RefBlk2 : vector_array (data_width-1 downto 0);
            signal Sad : vector_array2 (data_width downto 0);   
            signal lat_en : STD_LOGIC;                    -------------- future control for delay latches
            signal Dlat : vector_array (data_width-1 downto 0);






begin
-----------create the processing elements---------
        gen_pro_ele: for i in 0 to number_of_PE-1 generate
        Processing_Element : ProEle port map(                          CurBlk => CurBlk(i), ------- pins to wires or sinals 
                                                                             RefBlk1 => RefBlk1(i),
                                                                             RefBlk2 => RefBlk2(i),
                                                                             Sad => Sad(i),
                                                                             SEL => SEL,
                                                                             clk => clk,
                                                                             reset => reset,
                                                                             lat_en => lat_en,
                                                                             Dlat => Dlat(i));
                                                    end generate gen_pro_ele;




end Behavioral;

合成后的错误

第100行：指数值＆lt; 8＆gt;超出范围[7：0]的数组＆lt; curblk＆gt;

错误：HDLC编译器：1316-第101行：索引值＆lt; 8＆gt;超出范围[7：0]的数组＆lt; refblk1＆gt;

错误：HDLC编译器：1316-行102：索引值＆lt; 8＆gt;超出范围[7：0]的数组＆lt; refblk2＆gt;

错误：HDLC编译器：1316-第108行：索引值＆lt; 8＆gt;超出范围[7：0]的数组＆lt; dlat＆gt;

Line100是什么 - Processing_Element：ProEle端口映射（CurBlk =＆gt; CurBlk（i），-------引脚连线或阴影

Line101 - RefBlk1 =＆gt; RefBlk1（i）中，

Line102 - RefBlk2 =＆gt; RefBlk2（i）中，

Line108 - Dlat =＆gt; DLAT（I））;

我希望组件ProEle生成16次，输入（CurBlk，RefBlk1，RefBlk2）为8位宽。

The rtl schematic for ProEle component can be found in this link

我真正不理解的是合成工具产生错误的原因指数值＆lt; 8＆gt;超出范围[7：0]的数组＆lt; curblk＆gt;等等而不是生成16个ProEle组件实例，因为vector_array类型具有8bits（当前data_width）的自然范围，并且应该能够处理索引8-16，从而生成组件的16个实例。

Answer 1

package logic_array_type is
constant number_of_PE: integer := 16; -- number of processing elements   
constant    data_width: integer := 8; -- size of datapath, can be changed. 
type vector_array is array (natural range <>) of std_logic_vector(data_width-1 downto 0);--to allow use of signal as CurBlk(i) to connect to the ith generated instanciation of entity/component.
type vector_array2 is array (natural range <>) of std_logic_vector(data_width downto 0);

end package logic_array_type;

错误在包中。数组范围声明表明我使用向量的最大长度作为我想循环的次数。（自然范围＆lt;＆gt;）。而我在生成语句中要求循环次数超过这些次数.......

gen_pro_ele：for i in 0 to number_of_PE-1 generate。

因此有必要在包中改变（自然范围＆lt;＆gt;）到（0到number_of_PE）。

使用带有std_logic_vector

1 个答案: