使用ARM处理器(HPS)的DE1-SoC上的硬件加速算术逻辑单元(ALU)Linux应用

时间:2018-11-02 18:30:52

标签: c linux verilog mmap soc

我为ALU创建了一个Verilog文件,该文件具有以下操作:加,减,与和重置。然后,我将ALU与Avalon存储器从属接口包装在一起,以便ARM处理器可以通过H2F轻型桥接器专门访问它。然后,在完成mmap()之后,用户可以选择操作并为data1和data2输入值。结果将显示在终端上。 ALU中每个寄存器的偏移量均为4位。这意味着ALU中寄存器的基地址具有4位跨度。

我面临的问题是我似乎无法将值写入ALU寄存器(opcode,data1,data2)。我已经使用mmap()函数完成了正确的映射。但是,我得到的结果始终为0。

ALU Verilog代码如下所示。

module alu_avalon(
input clk,
input[1:0] opcode,
input[31:0] dataA,
input[31:0] dataB,
output[31:0] alu_result
);


assign alu_result =     (opcode == 0) ? 0               :
                        (opcode == 1) ? dataA + dataB   :
                        (opcode == 2) ? dataA - dataB   :
                                        dataA & dataB;

endmodule

然后,ALU封装有Avalon Memory Mapped从接口,如下面的Verilog编码所示。

module alu_avalon_top (
input reset,
input clk,
input chipselect,
input [1:0]address,
input write,
input [31:0]writedata,
output [31:0]readdata
);

wire [31:0]lineA;
wire [31:0]lineB;
wire [1:0]opcode;
wire [31:0]result_alu;

alu_avalon inst3 (
                    .clk(clk),
                    .opcode(opcode),
                    .dataA(lineA),
                    .dataB(lineB),
                    .alu_result(result_alu)
                    );

alu_interface inst2(

                    .clk        (clk),
                    .reset      (reset),
                    .chipselect (chipselect),
                    .address    (address),
                    .writedata  (writedata),
                    .readdata   (readdata),
                    .alu_result (result_alu),
                    .data1      (lineA),
                    .data2      (lineB),
                    .opcode     (opcode),
                    .write      (write)
                    );


endmodule

module alu_interface (
input reset,
input clk,
input chipselect,
input [1:0]address,
input write,
input [31:0]writedata,
output reg [31:0]readdata,
output reg[1:0]opcode,
output reg[31:0]data1,
output reg[31:0]data2,
input[31:0] alu_result

);

always @ (posedge clk or negedge reset)
begin

    if (reset == 0)
    begin
        readdata <= 0;
        data1 <= 0;
        data2 <= 0;
    end
    else 
    begin
        if(chipselect == 1 && write == 1)
        begin
            case (address)
                2'b00:      opcode <= writedata[1:0];
                2'b01:      data1 <= writedata;
                2'b10:      data2 <= writedata;
                default:    readdata <= alu_result;
            endcase
        end
    end
end

endmodule

我已经使用Qsys添加了自定义IP,并将avalon从站连接到H2F轻型桥AXI主站。

Qsys互连: Qsys interconnect map

Linux应用程序的C编码

#define HW_REGS_BASE ( ALT_LWFPGASLVS_OFST )
#define HW_REGS_SPAN ( 0x00200000 )
#define HW_REGS_MASK ( HW_REGS_SPAN - 1 )

volatile unsigned long *aluMap = NULL;
void *virtual_base;
int main(void){

    int fd;
    printf("Open memory map\n");
    if( ( fd = open( "/dev/mem", ( O_RDWR | O_SYNC ) ) ) == -1 ) {
        printf( "ERROR: could not open \"/dev/mem\"...\n" );
        return( 1 );
    }

    virtual_base = mmap( NULL, HW_REGS_SPAN , ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd, HW_REGS_BASE );

    if( virtual_base == MAP_FAILED ) {
        printf( "ERROR: mmap() failed...\n" );
        close( fd );
        return( 1 );
    }
    aluMap = (unsigned char *)(virtual_base + ALU8_0_BASE);
    printf("ALU addr: %x\n", aluMap);
    volatile unsigned int *opcode =(unsigned int*)(aluMap + 0x0);
    volatile unsigned int *data1 = (unsigned int*)(aluMap + 0x4);
    volatile unsigned int *data2 = (unsigned int*)(aluMap + 0x8);
    volatile unsigned int *result= (unsigned int*)(aluMap + 0xc);
    printf("op:%x\ndat1:%x\ndat2:%x\nresult:%x\n", opcode,data1,data2,result);
    int op;
    int dat1;
    int dat2;
    printf("operation code: ");
    scanf(" %d", &op);
    *opcode = op;
    printf("data1: ");
    scanf(" %d", &dat1);
    *data1 = dat1;
    printf("data2: ");
    scanf(" %d", &dat2);
    *data2 = dat2;
    int z = *result;
    printf("The result is %d\n", z);
    return 0;
}

输出为ALU output

有人可以告诉我在编码或连接方面做错了什么吗?已经进行了一个月的故障排除... IP寄存器的内存映射是否与没有寄存器的IP不同...或者我需要编写ALU内核驱动程序,以便Linux可以识别硬件ALU?

任何建议都值得赞赏。

1 个答案:

答案 0 :(得分:1)

非常感谢在线社区帮助我解决了我的问题。

如@Unn所指出的,

  
      
  • 写信号应仅用于写事务
  •   
  • 读取信号应仅用于读取事务
  •   在新的QSYS中不推荐使用
  • chipselect
  •   

我已经编辑了Verilog编码(分别进行读写交易并删除了ChipSelect),瞧,ALU的工作原理很吸引人。

always @ (posedge clk or negedge reset)
begin

    if (reset == 0)
    begin
        readdata <= 0;
        data1 <= 0;
        data2 <= 0;
    end
    else 
    begin
        if(write == 1)
        begin
            case (address)
                2'b00:  opcode <= writedata[1:0];
                /* OPCODE
                 1: ADD
                 2: SUB
                 3: AND   */
                2'b01:  data1 <= writedata;
                2'b10:  data2 <= writedata;
                default:    ;
            endcase
        end
        else if (read == 1)
        begin
            case (address)
                2'b00:  readdata <= opcode;
                2'b01:  readdata <= data1;
                2'b10:  readdata <= data2;
                2'b11:  readdata <= alu_result;
                default: readdata <= 0;
            endcase
        end
    end
end

要做的另一项更改是在main.c程序中将#define HW_REGS_BASE ( ALT_LWFPGASLVS_OFST )替换为#define HW_REGS_BASE ( ALT_STM_OFST )

下面是ALU输出端子

ALU output

特别感谢Rocketboard社区