Question

我正在尝试使用verilog进行VGA输出，但我似乎无法弄清r_hcount为何保持X。模拟波形显示r_vcount正确地重置为0，但是由于某种原因r_hcount从未重置为0。我不知道为什么...

Verilog代码：

module m_VGA640x480(
  input  wire        iw_clock,
  input  wire        iw_pix_stb,
  input  wire        iw_rst,
  output wire        ow_hs,
  output wire        ow_vs,
  output wire        ow_blanking,
  output wire        ow_active,
  output wire        ow_screenend,
  output wire        ow_animate,
  output wire  [9:0] ow_x,
  output wire  [9:0] ow_y
  );
  localparam HS_STA = 16;
  localparam HS_END = 16 + 96;
  localparam HA_STA = 16 + 96 + 48;
  localparam VS_STA = 480 + 11;
  localparam VS_END = 400 + 11 + 2;
  localparam VA_END = 480;
  localparam LINE   = 800;
  localparam SCREEN = 524;

  reg [9:0] r_hcount;
  reg [9:0] r_vcount;

  assign ow_hs = ~((r_hcount >= HS_STA) & (r_hcount < HS_END));
  assign ow_vs = ~((r_vcount >= VS_STA) & (r_vcount < VS_END));

  assign ow_x = (r_hcount <  HA_STA) ? 0 : (r_hcount - HA_STA);
  assign ow_y = (r_vcount >= VA_END) ? (VA_END - 1) : (r_vcount);

  assign ow_blanking = ((r_hcount < HA_STA) | (r_vcount > VA_END - 1));

  assign ow_active = ~((r_hcount < HA_STA) | (r_vcount > VA_END - 1));

  assign ow_screenend = ((r_vcount == SCREEN - 1) & (r_hcount == LINE));

  assign ow_animate = ((r_vcount ==VA_END - 1) & (r_hcount == LINE));

  always @(posedge iw_clock)
  begin
    if (iw_rst)
    begin
      r_hcount <= 0;
      r_vcount <= 0;
    end
    if (iw_pix_stb)
    begin
      if (r_hcount == LINE)
      begin
        r_hcount <= 0;
        r_vcount <= r_vcount + 1;
      end
      else
        r_hcount <= r_hcount + 1;

      if (r_vcount == SCREEN)
        r_vcount <= 0;
    end
  end
endmodule

这是模拟的结果。 r_hcount发生了错误...当重置为1时，代码应该将两个计数器都设置为0，但是由于某种原因，它没有被重置为0。请帮助。

Wavefrorm

Answer 1

从您的工作中，我注意到有一点可能会导致问题

import scala.language.higherKinds

case object True
type not[X] = X => Nothing

sealed trait Nat {
  // These dependent types are added because Scala doesn't support type-level
  // pattern matching, so this is a workaround. Nat is otherwise unchanged.
  type IsZero
  type IsOne
  type IsSucc
}
sealed trait Zero extends Nat {
  type IsZero = True.type
  type IsOne = Nothing
  type IsSucc = Nothing
}
sealed trait Succ[N <: Nat] extends Nat {
  type IsZero = Nothing
  type IsOne = N#IsZero
  type IsSucc = True.type
}

type One = Succ[Zero]

// These definitions should look familiar.
sealed trait Even[N <: Nat]
sealed case class Base() extends Even[Zero]
sealed case class Step[N <: Nat](evenN: Even[N]) extends Even[Succ[Succ[N]]]

// A version of scalaz.Leibniz.===, adapted from
// https://typelevel.org/blog/2014/07/02/type_equality_to_leibniz.html.
sealed trait ===[A <: Nat, B <: Nat] {
  def subst[F[_ <: Nat]](fa: F[A]): F[B]
}

implicit def eqRefl[A <: Nat] = new ===[A, A] {
  override def subst[F[_ <: Nat]](fa: F[A]): F[A] = fa
}

// This definition of evenness is easier to work with. We will prove (the
// important part of) its equivalence to Even below.
sealed trait _Even[N <: Nat]
sealed case class _Base[N <: Nat]()(
  implicit val nIsZero: N === Zero) extends _Even[N]
sealed case class _Step[N <: Nat, M <: Nat](evenM: _Even[M])(
  implicit val nIsStep: N === Succ[Succ[M]]) extends _Even[N]

// With this fact, we only need to prove not[_Even[One]] and not[Even[One]]
// will follow.
def `even implies _even`[N <: Nat]: Even[N] => _Even[N] = {
  case b: Base => _Base[Zero]()
  case s: Step[m] =>
    val inductive_hyp = `even implies _even`[m](s.evenN) // Decreasing on s
    _Step[N, m](inductive_hyp)
}

def `one is not zero`: not[One === Zero] = {
  oneIsZero =>
    type F[N <: Nat] = N#IsSucc
    oneIsZero.subst[F](True)
}

def `one is not _even` : not[_Even[One]] = {
  case base: _Base[One] =>
    val oneIsZero: One === Zero = base.nIsZero
    `one is not zero`(oneIsZero)
  case step: _Step[One, m] =>
    val oneIsBig: One === Succ[Succ[m]] = step.nIsStep
    type F[N <: Nat] = N#IsOne
    oneIsBig.subst[F](True)
}

def `one is odd`: not[Even[One]] =
  even1 => `one is not _even`(`even implies _even`(even1))

因此，如果发生姿势时钟，always @(posedge iw_clock) begin if (iw_rst) //you define r_hcount <= 0 here ..... if (iw_pix_stb) //<== another condition // r_hcount <= 0 is also defined here可能会在此处出现错误。我建议应该这样做

r_hcount

祝你好运。

Answer 2

在对代码进行了更多修改之后，我发现这是因为r_hcount <= 0被r_hcount <= r_hcount + 1覆盖，这会将r_hcount设置为X。这是因为两个时钟输入都是相同的频率。

将来我应该更加小心...

Verilog无法弄清楚为什么reg总是X

2 个答案: