Question

在我的makefile中，我想根据for循环中的变量包括其他一些makefile，这是否可能。

顶级Makefile：

CC          = gcc
CFLAGS      = -O0 -g3 -W -Wall -pedantic
LDFLAGS     =

DEFINES     =
PROJECT     = proj

INCLUDES    =
SOURCES     =

TEMP_PATH   := $(PROJECT)
include $(TEMP_PATH)/Makefile

$(for blocks in $(BLOCKS); do \
    include $$(blocks)/Makefile; \
done)

all : $(PROJECT).exe

$(PROJECT).exe :
    $(CC) $(CFLAGS) $(LDFLAGS) $(DEFINES) $(INCLUDES) $(SOURCES) -o $@

clean :
    rm -rf *.exe

proj / Makefile：

CC          =   gcc
CFLAGS      = -O0 -g3 -W -Wall -pedantic
LDFLAGS     = 

DEFINES     =  

BLOCKS      := std_communication

INCLUDES    := $(INCLUDES) -I $(TEMP_PATH)/Utils
INCLUDES    := $(INCLUDES) -I $(TEMP_PATH)/Communication

SOURCES     := $(SOURCES) $(wildcard $(TEMP_PATH)/Utils/*.c)
SOURCES     := $(SOURCES) $(wildcard $(TEMP_PATH)/Communication/*.c)
SOURCES     := $(SOURCES) $(wildcard $(TEMP_PATH)/main.c)

for循环外的语法似乎是错误的。

Answer 1

您不能这样写，但您可以这样写：

include $(addsuffix /Makefile,$(BLOCKS))

Makefile：包含在循环中/在目标外部循环

1 个答案: