Question

我正在尝试在verilog中实现JK触发器的简单FSM。但是，我看到输出“ q”和“ q_not”在多个时间点都是错误的。我在下面介绍代码和输出。可以让我知道代码有什么问题吗？我特别想知道这种实现有什么问题，即使还有其他方法可以实现JK触发器。

JK触发器和测试平台的模块

`timescale 1ns/100ps

module jk_ff(j, k, clk, reset, q, q_not);

input j, k, clk, reset;

output reg q, q_not;

reg present_state, next_state;

parameter state_a = 1'b0;
parameter state_b = 1'b1;

always @ (present_state or j or k)
begin:comb_logic

 next_state = state_a;
 //next_state = 0;

 case(present_state)

  state_a: begin
   if (j == 1'b0 && k == 1'b0) begin
     next_state = state_a;
     end
   else if (j == 1'b0 && k == 1'b1) begin
     next_state = state_a;
     end
   else if (j == 1'b1 && k == 1'b0) begin
     next_state = state_b;
     end
   else if (j == 1'b1 && k == 1'b1) begin
     next_state = state_b;
     end
   end

  state_b: begin
   if (j == 1'b0 && k == 1'b0) begin
     next_state =  state_b;
   end
   else if (j == 1'b0 && k == 1'b1) begin
     next_state = state_a;
   end
   else if (j == 1'b1 && k == 1'b0) begin
     next_state = state_b;
   end
   else if (j == 1'b1 && k == 1'b1) begin
     next_state = state_a;
   end
  end
  default: next_state = state_a;
 endcase 
end

always @ (posedge clk or reset)
begin: seq_logic

if (reset) begin
 q <= 1'b0;
 q_not <= 1'b1;
 present_state <= state_a;
 end
 else begin
 present_state <= next_state;

 case(present_state)

   state_a: begin
    q <= 1'b0;
    q_not <= 1'b1;
   end
   state_b: begin
    q <= 1'b1;
    q_not <= 1'b0;
   end
   default: present_state <= state_a;

  endcase
  end
 end

endmodule

//testbench

module jk_ff_tb;

reg j, k, clk, reset;

wire q, q_not;

jk_ff DUT(.j(j), .k(k), .clk(clk), .reset(reset), .q(q), .q_not(q_not));

initial begin
clk =0;
forever #5 clk = !clk;
end

initial begin
 $monitor("j = %b, k = %b, q = %b, q_not = %b", j, k, q, q_not);
 $dumpfile("jk_ff_wave.vcd");
 $dumpvars;
 reset = 1;
 j=1'b0;
 k=1'b1;
#10 reset = 0;

 #15 j=1'b1;
 #15 k=1'b0;
 #15 j=1'b0;
 #15 k=1'b1;
 #15 j=1'b1;
 #15 k=1'b1;


 #10 $finish;  

end

endmodule

测试台模拟的输出，显示输入和主要输出的值

j = 0, k = 1, reset = 1, q = 0, q_not = 1
j = 0, k = 1, reset = 0, q = 0, q_not = 1
j = 1, k = 1, reset = 0, q = 0, q_not = 1
j = 1, k = 1, reset = 0, q = 1, q_not = 0
j = 1, k = 0, reset = 0, q = 1, q_not = 0
j = 1, k = 0, reset = 0, q = 0, q_not = 1
j = 0, k = 0, reset = 0, q = 1, q_not = 0
j = 0, k = 1, reset = 0, q = 1, q_not = 0
j = 1, k = 1, reset = 0, q = 0, q_not = 1
j = 1, k = 1, reset = 0, q = 1, q_not = 0
j = 1, k = 1, reset = 0, q = 0, q_not = 1

enter code here

谢谢！

Answer 1

您这里遇到各种各样的问题：

在seq_logic中，为present_state分配 blocking 分配，下一条语句为case(present_state)。这将测试present_state的 old 值，这不是您想要的
您的'comb_logic'过程对present_state敏感，但是您的seq_logic过程在时钟上升沿改变present_state。乍一看，这似乎是正确的做法，但事实并非如此-将其绘制出来。 comb_logic的编写方式应该仅对J和K

这两个足以获得正确的结果，但这对于JK来说太复杂了-重新开始，将所有内容放入一个时钟处理的进程中，转储下一个逻辑进程，仅使用JK的行为-加载，设置，或切换。您还应该将当前时间添加到$monitor中。

JK触发器状态图实现的错误输出

1 个答案: