我希望有两个组合过程以有线或样式驱动一个信号。每个过程都可以将“ Z”或“ 1”值驱动到信号,并且全局下拉至“ L”。
Vivado 2017.1综合“优化”了我的代码,以将常数0驱动到输出端口。为什么会这样?如何解决此问题?
代码:
library ieee;
use ieee.std_logic_1164.all;
entity test is
port(
input_0 : in std_logic;
input_1 : in std_logic;
output : out std_logic
);
end entity test;
architecture rtl of test is
signal s_output : std_logic;
begin
output <= to_X01(to_bit(s_output));
process(input_0)
begin
s_output <= 'Z';
if input_0='1' then
s_output <= '1';
end if;
end process;
process(input_1)
begin
s_output <= 'Z';
if input_1='1' then
s_output <= '1';
end if;
end process;
s_output <= 'L';
end architecture rtl;
综合结果:
WARNING: [Synth 8-3917] design test has port output driven by constant 0