Verilog - “case”阻止

Question

我正在尝试使用verilog在vivado 2017.4中使用NEXYS 4 DDR制作一个4位全加器。全加器工作正常，现在我正在设置驱动板上7-seg显示器的阳极。我使用了“case”块，计数器用于减慢信号速度。我在第三个syntax error near end块结尾的end处收到always错误

`timescale 1ns / 1ps

模块FA（     输入clk_i，

input [3:0] A,
input [3:0] B,
input C_in,
output [3:0] S,
output C_o
);
reg [19:0] counter;
reg [7:0] anode;
wire [0:0] MSB;
reg [4:0] C;
integer i;
genvar k;
reg temp [4:0];
always@(*)
begin
if(C_in)
begin
C[0] = 1'b1;
end
else begin
C[0] = 1'b0;
end
for(i=0;i<=3;i=i+1)
begin
temp[i] = A[i] + B[i] + C[i];
if((A[i] && B[i]) || (A[i] && C[i]) || (B[i] && C[i]))
begin
C[i+1] = 1'b1;
end
else begin
C[i+1] = 1'b0;
end
end

end
for(k=0;k<=3;k=k+1)
begin
assign S[k] = temp[k];
end
assign C_o = C[4];

always@(posedge clk_i)
begin
counter <= counter + 1;
end

assign MSB = counter[19];

always@(*)
begin
    case(MSB)
        1'b0: begin
        anode = 8'b11101111;
              end
        1'b1: begin
        anode = 8'b11011111;
              end
end //this line gives me the error

endmodule

Answer 1

您错过了endcase关键字：

always@(*)
begin
    case(MSB)
        1'b0: begin
        anode = 8'b11101111;
              end
        1'b1: begin
        anode = 8'b11011111;
              end
    endcase
end

使用case语句进行1位选择是过度的。

wire [7:0] anode = (MSB) ? 8'b1101_1111 : 8'b1110_1111;