Question

我一直在解决使用VHDL解决错误“标识符类型与其用法不一致”的问题。据我所知，这意味着在分配值时出现了问题。例如，将std_logic分配给std_logic_vector或者将std_logic分配给某个位。正确的吗？

我尝试进行端口映射后得到错误。这是错误发生的地方：

LIBRARY ieee; 
USE ieee.std_logic_1164.all; 
USE ieee.std_logic_1164.all; 
USE  IEEE.STD_LOGIC_ARITH.all;
USE  IEEE.STD_LOGIC_UNSIGNED.all;        
ENTITY ALU1 IS
 PORT (a,b,ainverse,binverse, cin:IN std_logic;
    operation: IN std_logic;
        cout, result,resolution : OUT std_logic
   );
 END ALU1;


ARCHITECTURE archAl OF ALU1 IS

COMPONENT adder
    PORT(a,b, cin: IN std_logic;
            cout,resolution: OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT(a, b :IN std_logic;
        resolution: OUT std_logic);
END COMPONENT;

COMPONENT OR1
    PORT(a, b : IN std_logic;
        resolution: OUT std_logic);
END COMPONENT;

COMPONENT mux2
 PORT( a, inverse : IN std_logic;
            resolution  :   OUT std_logic
 );
END COMPONENT;

COMPONENT XOR1
 PORT(a,b : IN std_logic;
     resolution : OUT std_logic
     );
END COMPONENT;

 --SIGNAL resolution: std_logic;



BEGIN --ARCHITECTURE BEGIN
andA:  mux2 PORT MAP(a, ainverse, resolution);
andB:  mux2 PORT MAP(b, binverse, resolution);
 resolutionAnd: AND1 PORT MAP (andA, andB, resolution);
  addA: mux2 PORT MAP(a, ainverse, resolution);
addB: mux2 PORT MAP(b, binverse, resolution);
    resolutionOr: OR1 PORT MAP (a, b, resolution);

    resolutionAdd: adder PORT MAP(ainverse, binverse, cin, cout, resolution);

resolutionXor: XOR1 PORT MAP (a,b, resolution);
PROCESS(operation, a, ainverse, resolution, b, cin,cout, BINVERSE) is
BEGIN --PROCESS BEGIN
 IF operation = "00" THEN
    result<=resolutionAnd;
 ELSIF operation = "01" THEN

    result<=resolutionOr;
 ELSIF operation = "10" THEN

     result<=resolutionAdd;

ELSIF operation ="11" THEN

     result<=resolutionAXor;
 END IF;

END PROCESS;
END archAl;

错误发生在resolutionAnd: AND1 PORT MAP (andA, andB, resolution);

中

我得到Error (10476): VHDL error at alu.vhd(158): type of identifier "andA" does not agree with its usage as "std_logic" type和Error (10476): VHDL error at alu.vhd(158): type of identifier "andB" does not agree with its usage as "std_logic" type。因此，搜索影响andA的Mux2和B以查看分配的类型之间是否存在不一致是合乎逻辑的。

mux2的代码是：

ENTITY mux2 IS
PORT(a, inverse: IN std_logic;
   resolution       :   OUT std_logic);
END mux2;

ARCHITECTURE archMux2 OF mux2 IS
  BEGIN
     PROCESS(a, inverse)
     BEGIN
         IF inverse = '0' THEN
            resolution <= a;
         ELSE
            resolution <= NOT a;
        END IF;
     END PROCESS;
 END archMux2;

我无法检测到指定类型中的任何不一致。所以我想我没有正确理解错误或发生了错误，我不知道。有人可以协助吗？

Answer 1

push和-f是标签：

andA

您似乎已将它们连接到andB组件andA: mux2 PORT MAP(a, ainverse, resolution); andB: mux2 PORT MAP(b, binverse, resolution); ^^^^的端口：

AND

错误“标识符的类型与其用法不一致”“类型”在VHDL中是什么意思？端口映射会影响“类型”吗？

1 个答案: