Process Statement必须包含wait语句 - 当WAIT FOR timeperiod存在时

Question

错误：

Error (10533): VHDL Wait Statement error at DE0.vhd(276): Wait Statement must 
contain condition clause with UNTIL keyword.

Error (10442): VHDL Process Statement error at DE0.vhd(271): Process Statement 
must contain either a sensitivity list or a Wait Statement

我是VHDL的新手。致力于DE0 FPGA和Quartus II。我的代码包含一个等待语句，但在编译时仍然抛出错误。

    q3:PROCESS 
    BEGIN

        IF button(2) = '0' AND pb_flag = '0' THEN
            pb_flag <= '1';
            WAIT FOR 20 ms;
        END IF;

        IF pb_flag = '1' AND button(2)='1' THEN
            count_1 <= count_1 + 1;
            pb_flag <= '0';
            WAIT FOR 10 ns;
        END IF;

        IF button(1)='0' THEN
            count_1 <= 0;
            WAIT FOR 10 ns;
        END IF;
        WAIT FOR 10 ns;
    END PROCESS q3;

我正在尝试计算按下按钮的次数，按钮（2），使用按钮（1）作为重置。稍后将在7段显示输出。知道为什么吗？