wait必须包含带有until子句的条件子句

时间:2015-02-14 00:38:38

标签: vhdl

以下VHDL用于测试展位乘数。在分析和详细说明期间,我在第一个等待语句中一直收到错误:“wait语句必须包含条件子句,直到关键字” 我有几个以这种方式编写的工作测试台(即信号分配,等待x ns,其他分配,等待x ns ......)。我似乎无法找到错误可能是什么。

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY BoothMultiplier_32_test IS
END BoothMultiplier_32_test;

ARCHITECTURE test_arch OF BoothMultiplier_32 IS

SIGNAL A_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL B_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL result_test  :   STD_LOGIC_VECTOR (63 downto 0);

COMPONENT BoothMultiplier_32
    PORT (
        dataA, dataB    :   IN STD_LOGIC_VECTOR (31 downto 0);
        result          :   OUT STD_LOGIC_VECTOR (63 downto 0)
    );
END COMPONENT;

BEGIN
    DUT1: BoothMultiplier_32 
    PORT MAP(
        dataA=>A_test,
        dataB=>B_test,
        result=>result_test
    );

    testing : PROCESS
    BEGIN
        wait for 10 ns;
        A_test<=x"0000000A";
        B_test<=x"0000000A";
        --wait for 10 ns;
        --A_test<=x"10000000";
        --B_test<=x"00000010";
        --wait for 10 ns;
        --A_test<=x"FFFFFFFF";
        --B_test<=x"FFFFFFFF";
        wait;
    END PROCESS testing;

END ARCHITECTURE test_arch;

1 个答案:

答案 0 :(得分:0)

代码中唯一可观察到的错误是:

ARCHITECTURE test_arch OF BoothMultiplier_32 IS

应该是:

ARCHITECTURE test_arch OF BoothMultiplier_32_test IS

使用虚拟BoothMultiplier_32在您的实体和体系结构对之前并使用上述更正:

library ieee;
use ieee.std_logic_1164.all;

entity boothmultiplier_32 is
    port (
        dataa, datab    :   in std_logic_vector (31 downto 0);
        result          :   out std_logic_vector (63 downto 0)
    );
end entity;

architecture foo of boothmultiplier_32 is
begin
end architecture;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY BoothMultiplier_32_test IS
END BoothMultiplier_32_test;

ARCHITECTURE test_arch OF BoothMultiplier_32_test IS

SIGNAL A_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL B_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL result_test  :   STD_LOGIC_VECTOR (63 downto 0);

COMPONENT BoothMultiplier_32
    PORT (
        dataA, dataB    :   IN STD_LOGIC_VECTOR (31 downto 0);
        result          :   OUT STD_LOGIC_VECTOR (63 downto 0)
    );
END COMPONENT;

BEGIN
    DUT1: BoothMultiplier_32 
    PORT MAP(
        dataA=>A_test,
        dataB=>B_test,
        result=>result_test
    );

    testing : PROCESS
    BEGIN
        wait for 10 ns;
        A_test<=x"0000000A";
        B_test<=x"0000000A";
        --wait for 10 ns;
        --A_test<=x"10000000";
        --B_test<=x"00000010";
        --wait for 10 ns;
        --A_test<=x"FFFFFFFF";
        --B_test<=x"FFFFFFFF";
        wait;
    END PROCESS testing;

END ARCHITECTURE test_arch;

然后代码使用详细说明并运行目标boothMultiplier_32_test进行分析,详细说明和运行(虽然没有做任何有趣的事情但是显示正确的连接性)。

也许您可以告诉我们您遇到问题的工具是什么?