算术右移后我可以减少位数吗？

Question

如果我在verilog中减少算术右移后的位数，我还能得到正确的有符号数吗？这有效吗？

减少的位数=移位值

A = 1110_1110
A>>>1
new A = 111_0111  

Answer 1

是的，但你应该使用三个'＆gt;'不是四个，当然新的变量应该足够大：

wire signed [7:0] A,B;
wire signed [6:0] just_fits;
wire signed [5:0] oops;

  assign         B = A >>> 1;  // Signed divide by two
  assign just_fits = A >>> 1;  // Signed divide by two
  assign      oops = A >>> 1;  // Goes wrong