所以我疯狂地试图解决这个问题。我有一个具有通用宽度的ALU，我对ALU的所有操作都有效，但我无法让它为空操作插槽返回0。
赋值的关键是使用std_logic_arith和std_logic_unsigned包。我有另一个ALU设置使用numeric_std包，它正确地发送0用于其他操作。
以下是适用于numeric_std包的代码：
when C_EMPTY1 =>
temp := std_logic_vector(unsigned'(resize("0",WIDTH)));
output <= temp;
以下是我正在尝试使用不起作用的ALU：
when C_EMPTY2 =>
temp := std_logic_vector(conv_unsigned(0, WIDTH));
output <= temp;
对于不工作的ALU，它会继续返回上一个操作的操作结果。
对不起，这是他们的宣布方式：
variable temp : std_logic_vector(WIDTH-1 downto 0);
output : out std_logic_vector(WIDTH-1 downto 0);
以下是整个计划：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alu_sla is
generic (
WIDTH : positive := 16
);
port (
input1 : in std_logic_vector(WIDTH-1 downto 0);
input2 : in std_logic_vector(WIDTH-1 downto 0);
sel : in std_logic_vector(3 downto 0);
output : out std_logic_vector(WIDTH-1 downto 0);
overflow : out std_logic
);
end alu_sla;
-- Define an ALU using std_logic_arith and std_logic_unsigned
architecture STR of alu_sla is
constant C_ADD : std_logic_vector(3 downto 0) := "0000";
constant C_SUB : std_logic_vector(3 downto 0) := "0001";
constant C_MULT : std_logic_vector(3 downto 0) := "0010";
constant C_AND : std_logic_vector(3 downto 0) := "0011";
constant C_OR : std_logic_vector(3 downto 0) := "0100";
constant C_XOR : std_logic_vector(3 downto 0) := "0101";
constant C_NOR : std_logic_vector(3 downto 0) := "0110";
constant C_NOT_IN1 : std_logic_vector(3 downto 0) := "0111";
constant C_SHIFTL1_IN1 : std_logic_vector(3 downto 0) := "1000";
constant C_SHIFTR1_IN1 : std_logic_vector(3 downto 0) := "1001";
constant C_SWAP_HIGHLOW_IN1 : std_logic_vector(3 downto 0) :=
"1010";
constant C_REVERSE_BITS_IN1 : std_logic_vector(3 downto 0) :=
"1011";
constant C_EMPTY1 : std_logic_vector(3 downto 0) := "1100";
constant C_EMPTY2 : std_logic_vector(3 downto 0) := "1101";
constant C_EMPTY3 : std_logic_vector(3 downto 0) := "1110";
constant C_EMPTY4 : std_logic_vector(3 downto 0) := "1111";
function Reverse (x : std_logic_vector) return std_logic_vector is
alias alx : std_logic_vector (x'length - 1 downto 0) is x;
variable y : std_logic_vector (alx'range);
begin
for i in alx'range loop
y(i) := alx (alx'left - i);
end loop;
return y;
end;
function CheckMultSize (x : std_logic_vector) return std_logic is
begin
for i in WIDTH to WIDTH*2-1 loop
if(x(i) = '1') then
return '1';
end if;
end loop;
return '0';
end;
begin -- STR
process(input1, input2, sel)
variable temp : std_logic_vector(WIDTH-1 downto 0);
variable temp_add : std_logic_vector(WIDTH downto 0);
variable temp_mult : std_logic_vector((WIDTH*2-1) downto 0);
begin
--defaults
overflow <= '0';
case sel is
when C_ADD =>
temp_add := conv_std_logic_vector(unsigned(input1),
WIDTH+1) +
conv_std_logic_vector(unsigned(input2),
WIDTH+1);
output <= temp_add(WIDTH-1 downto 0);
overflow <= temp_add(WIDTH);
when C_SUB =>
temp := std_logic_vector(unsigned(input1)) -
std_logic_vector(unsigned(input2));
output <= temp;
when C_MULT =>
temp_mult := std_logic_vector(unsigned(input1)) *
std_logic_vector(unsigned(input2));
if (CheckMultSize(temp_mult) = '1') then
overflow <= '1';
else
overflow <= '0';
end if;
output <= temp_mult(WIDTH-1 downto 0);
when C_AND =>
temp := input1 and input2;
output <= temp;
when C_OR =>
temp := input1 or input2;
output <= temp;
when C_XOR =>
temp := input1 xor input2;
output <= temp;
when C_NOR =>
temp := input1 nor input2;
output <= temp;
when C_NOT_IN1 =>
temp := not input1;
output <= temp;
when C_SHIFTL1_IN1 =>
overflow <= input1(WIDTH-1);
temp := std_logic_vector(shl(unsigned(input1),
conv_unsigned(1, 1)));
output <= temp;
when C_SHIFTR1_IN1 =>
temp := std_logic_vector(shr(unsigned(input1),
conv_unsigned(1, 1)));
output <= temp;
when C_SWAP_HIGHLOW_IN1 =>
temp := (input1(WIDTH/2-1 downto 0) & input1(WIDTH-1
downto WIDTH/2));
output <= temp;
when C_REVERSE_BITS_IN1 =>
temp := Reverse(input1);
output <= temp;
when C_EMPTY1 =>
temp := (others => '0');
output <= std_logic_vector(conv_unsigned(0, WIDTH));
when C_EMPTY2 =>
temp := std_logic_vector(conv_unsigned(0, WIDTH));
output <= temp;
when C_EMPTY3 =>
temp := std_logic_vector(conv_unsigned(0, WIDTH));
output <= temp;
when C_EMPTY4 =>
temp := std_logic_vector(conv_unsigned(0, WIDTH));
output <= temp;
when others => null;
end case;
end process;
end STR;
我所要做的就是让C_EMPTY案例将0返回到输出，但是我不能这样做。