Question

我在VLSI中创建一个CPU，从寄存器开始：

private async void Page_Loaded(object sender, RoutedEventArgs e)
{
    DTO dto = new DTO { text = "My text" };

    MyContentDialog dialog = new MyContentDialog(dto);
    await dialog.ShowAsync();

    await new MessageDialog("My text, after being edited by the user in MyContentDialog: " + dto.text).ShowAsync();
}

我得到了语法检查器不会发生的奇怪错误，例如为什么我需要一个进程的“PORT”关键字。

来自Electric的完整日志：

library ieee;   
use ieee.std_logic_1164.all;

package types is
    type BYTE is array (7 downto 0) of std_logic;
end types;

-- Have to use one file because of Electric's compiler
library ieee;
use ieee.std_logic_1164.all; use work.types.all;

entity reg8 is
    port (
        clock   : in std_logic;
        inc     : in std_logic;
        dec     : in std_logic;
        store   : in std_logic;
        input   : in BYTE;
        output  : out BYTE
    );
end reg8;

architecture rtl of reg8 is
    signal state : BYTE;
begin
    tick : process(clock) is
    begin
        if(rising_edge(clock)) then
            if inc = '1' then
                state(0) <= not state(0);
                state(1) <= state(0) xor state(1);
                state(2) <= (state(0) and state(1)) xor state(2);
                state(3) <= (state(0) and state(1) and state(2)) xor state(3);
                state(4) <= (state(0) and state(1) and state(2) and state(3)) xor state(4);
                state(5) <= (state(0) and state(1) and state(2) and state(3) and state(4)) xor state(5);
                state(6) <= (state(0) and state(1) and state(2) and state(3) and state(4) and state(5)) xor state(6);
                state(7) <= (state(0) and state(1) and state(2) and state(3) and state(4) and state(5) and state(6)) xor state(7);
            elsif dec = '1' then
                state(0) <= not state(0);
                state(1) <= state(0) xnor state(1);
                state(2) <= (state(0) or state(1)) xnor state(2);
                state(3) <= (state(0) or state(1) or state(2)) xnor state(3);
                state(4) <= (state(0) or state(1) or state(2) or state(3)) xnor state(4);
                state(5) <= (state(0) or state(1) or state(2) or state(3) or state(4)) xnor state(5);
                state(6) <= (state(0) or state(1) or state(2) or state(3) or state(4) or state(5)) xnor state(6);
                state(7) <= (state(0) or state(1) or state(2) or state(3) or state(4) or state(5) or state(6)) xnor state(7);
            elsif store = '1' then
                state <= input;
            end if;
        end if;
        output <= state;
    end process tick;
end architecture rtl;

我正在使用电子超大规模集成电路（VLSI），可在http://www.staticfreesoft.com/index.html获得，以防有人想要尝试这一点。

Answer 1

你问，所以：

这似乎是＆＃34; Electric＆＃34;不是通用的VHDL编译器。它只支持某个子集和结构。即你想要做的事可能不会奏效。您需要切换到更好的＆＃34;（和付费）ASIC综合工具，如Synopsys工具。

使用传统晶体管实现ASIC编译器制作的电路可能需要大量的晶体管。它甚至可能无法正常工作，因为ASIC设计程序通常需要非常特定的晶体管特性。使用（C）PLD或一些逻辑门芯片（7400系列）来实现您的设计要容易得多。

在VLSI中编译VHDL时出错

1 个答案: