Question

我正在尝试在vhdl上为RAM 16 * 4编写代码，代码是：

entity RAM_16_4 is
Port ( clk : in  STD_LOGIC;
       WR : in  STD_LOGIC;
       add : in  STD_LOGIC_VECTOR (3 downto 0);
       Di : in  STD_LOGIC_VECTOR (3 downto 0);
       Do : out  STD_LOGIC_VECTOR (3 downto 0));
end RAM_16_4;

architecture Behavioral of RAM_16_4 is

type RAM is array (15 downto 0) of std_logic_vector (3 downto 0);
 signal int : STD_LOGIC_VECTOR (3 downto 0);
 signal x : STD_LOGIC_VECTOR (3 downto 0);
begin

process (clk,WR)
begin

if ( clk'event and clk='1') then
if ( WR='1') then
int<= conv_integer (add);
int<= Di;
end if;
x<=add;
end if;
end process;

x<= conv_integer (add);
Do<= x;

end Behavioral;

这是即将发生的错误： int的类型与conv_integer的类型不兼容。

我该怎样摆脱这个错误？

Answer 1

conv_integer将std_logic_vector转换为integer。您无法将integer分配给std_logic_vector。如果要将conv_integer分配给add或int，为什么要使用x？它们都是同一类型......

更重要的是：请注意conv_integer是非标准化包std_logic_arith或std_logic_unsigned的一部分，您不应该使用它们。相反，您应该使用标准化程序包to_integer(unsigned(...))中的numeric_std。

为FPGA实现RAM时，应参考FPGA制造商手册。例如来自Xilinx Synthesis User Guide

-- Single-Port RAM with Asynchronous Read (Distributed RAM)
-- File: rams_dist.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity rams_dist is
    port(
        clk : in std_logic;
        we : in std_logic;
        a : in std_logic_vector(5 downto 0);
        di : in std_logic_vector(15 downto 0);
        do : out std_logic_vector(15 downto 0)
    );
end rams_dist;

architecture syn of rams_dist is
    type ram_type is array (63 downto 0) of std_logic_vector(15 downto 0);
    signal RAM : ram_type;
begin
    process(clk)
    begin
        if (clk'event and clk = '1') then
            if (we = '1') then
                RAM(conv_integer(a)) <= di;
            end if;
        end if;
    end process;
    do <= RAM(conv_integer(a));
end syn;

......好吧，废话.... Xilinx也在使用错误的转换功能。让我们将其重写为标准化代码：

-- Single-Port RAM with Asynchronous Read (Distributed RAM)
-- File: rams_dist.vhd
library ieee;
use ieee.std_logic_1164.all;

entity rams_dist is
    port(
        clk : in std_logic;
        we : in std_logic;
        a : in std_logic_vector(5 downto 0);
        di : in std_logic_vector(15 downto 0);
        do : out std_logic_vector(15 downto 0)
    );
end rams_dist;

architecture syn of rams_dist is
    use ieee.numeric_std.all;
    type ram_type is array (2**a'length-1 downto 0) of std_logic_vector(di'length-1 downto 0);
    signal RAM : ram_type := (others => (others => '0')); -- let's initialize it at zeros
begin
    ram_proc: process(clk)
    begin
        if rising_edge(clk) then
            if we = '1' then
                RAM(to_integer(unsigned(a))) <= di;
            end if;
        end if;
    end process;
    do <= RAM(to_integer(unsigned(a)));
end syn;

请求帮助vhdl错误

1 个答案: