Question

我正在使用Spartan 6 FPGA在VHDL中设计一个简单的密码锁设计。这个错误出现了，我有点困惑，我怎么能解决它。我已经“搜索”了这个并根据这个帖子中的答案Too many comps of type “BUFGMUX” found to fit this device我相信我知道这个问题，但我不确定如何解决它。

现在纠正我，如果我错了，但我相信这个错误是由于我的设计中的以下代码

--clock divider
process(cclk,clr)
begin   
    if (clr ='1') then
        Count200Hz <= X"00000";
        --clk200     <= '0';
        temp       <= '0';
    elsif rising_edge(cclk) then
        if (Count200Hz = clk200HzEndVal) then
            clk200     <= not temp;
            Count200Hz <= X"00000";
        else
            Count200Hz <= Count200Hz + '1';
        end if;
    end if;
end process;

-- 2-bit counter
process(cclk,clr)
begin
    if clr = '1' then
        s <= "00";
    elsif rising_edge(cclk) then
        s <= s+1;
    end if;
end process;

--state machine
    state_mach:PROCESS(lclk, clr)
    BEGIN
        IF clr = '1' THEN
            present_state <= idle;
        ELSIF rising_edge(lclk) THEN
            present_state <= next_state;
        end if;
    END PROCESS;

    pulse_process: process(cclk, rst)
    begin
        if rst = '0' then
            pulse <= '0';
            count <= 0;
            current_state <= idle;
        elsif (rising_edge(cclk))then
            current_state <= next_state;
....

这些代码来自我设计中的不同vhdl模块。 ise是否认为我的设计中使用了三种不同的时钟，因此错误被抛出？

问题在于它们是不同的时钟，但它们源于系统时钟，时钟频率较低，一个是时钟脉冲。为了清晰起见，我添加了我的顶级设计

感谢任何帮助

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity simpleLock_top is
Port ( 
    mclk  : in   STD_LOGIC;
    rst   : in   STD_LOGIC;
    btnl  : in   STD_LOGIC;
    btnr  : in   STD_LOGIC;
    sw    : in   STD_LOGIC_VECTOR (3 downto 0);
    seg7  : out  STD_LOGIC_VECTOR (6 downto 0);
    an    : out  STD_LOGIC_VECTOR (3 downto 0);
    led   : out  STD_LOGIC_VECTOR (7 DOWNTO 0);
    dp    : out  STD_LOGIC);
    end simpleLock_top;

architecture Behavioral of simpleLock_top is

component x7seg_msg is
Port ( 
    x    : in   STD_LOGIC_VECTOR (15 downto 0);
    cclk : in   STD_LOGIC;
    clr  : in   STD_LOGIC;
    seg7 : out  STD_LOGIC_VECTOR (6 downto 0);
    an   : out  STD_LOGIC_VECTOR (3 downto 0);
    dp   : out  STD_LOGIC);
end component;

component clkdiv is
Port (
    cclk   : in  STD_LOGIC;
    clr    : in  STD_LOGIC;
    clk200 : out STD_LOGIC);
end component;

component simpleLock is
PORT (
    lclk   : IN  STD_LOGIC;
    clr   : IN  STD_LOGIC;
    btnl  : IN  STD_LOGIC;
    btnr  : IN  STD_LOGIC;
    code  : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
    sw    : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
    led   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    digit : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    user_input : OUT STD_LOGIC_VECTOR(15 downto 0));
end component;

component clock_pulse is
PORT ( 
    cclk  : IN  STD_LOGIC;
    rst   : IN  STD_LOGIC;
    trig  : IN  STD_LOGIC;
    pulse : OUT STD_LOGIC);
end component;

constant code : STD_LOGIC_VECTOR(15 downto 0):= X"1234";
signal digit: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal user_input : std_logic_vector(15 downto 0);
signal clk200, clkp, btn01: STD_LOGIC;
signal btn : STD_LOGIC_VECTOR(1 DOWNTO 0);
begin
    btn(0) <= btnr;
    btn(1) <= btnl;
    btn01  <= btn(0) or btn(1);
    --led <= X"00";

    V1: clkdiv
        port map(
            cclk   => mclk,
            clr    => rst,
            clk200 => clk200);

    V2: x7seg_msg
        port map(
            x    => user_input,
            cclk => clk200,
            clr  => rst,
            seg7 => seg7,
            an   => an,
            dp   => dp );

    V3: simpleLock
        port map(
            lclk  => clkp, 
            clr   => rst, 
            btnl  => btnl,
            btnr  => btnr,
            code  => code,
            sw    => sw,
            led   => led,
            digit => digit,
            user_input => user_input);

    V4: clock_pulse
        port map(
            cclk  => clk200,
            rst   => rst,
            trig  => btn01,
            pulse => clkp);
end Behavioral;

Answer 1

时钟启用

在FPGA设计中，通常最好使用可能性较小的不同时钟。

如果“clock_pulse”模块产生一个周期时钟脉冲，请不要将此脉冲用作时钟（代码中为“clkp”），而应用作时钟使能（下面代码中的“启用”）。 / p>

myproc : process(clk, rst)
begin
  if rst = '1' THEN
    -- your asynchronously reseted signals
  elsif rising_edge(clk) THEN
    if enable = '1' then
      -- things that must be done when you get the one cycle pulse
    end if;
  end if;
end process;

但要照顾任何非管理时钟域的交叉......

希望这有帮助。

地址：VHDL中1108错误（帮助）

1 个答案: