Question

如何使用CPLD（即Coolrunner II Pro）在VHDL中实现脉冲计数器和移位寄存器（用于滚动显示值）。

最终产品是一种数字频率计，能够测量100 - 100kHz之间的频率

Answer 1

我假设您正在寻找它来测量输入脉冲的持续时间。

有一个frequency measurement vhdl code here with testbench and explanation也是如此。请参阅下面的代码，有关更多信息，请转到链接。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_counter is
port (   DAT_O : out unsigned(47 downto 0);
         ERR_O : out std_logic;  --This is '1' if the pulse freq is more than clk freq.
         Pulse_I : in std_logic;   
         CLK_I : in std_logic
     );
end pulse_counter;
architecture Behavioral of pulse_counter is
signal Curr_Count,Prev_Count : unsigned(47 downto 0):=(others => '0');

begin

--Increment Curr_Count every clock cycle.This is the max freq which can be measured by the module.
process(CLK_I)
begin
    if( rising_edge(CLK_I) ) then
        Curr_Count <= Curr_Count + 1; 
    end if; 
end process;
--Calculate the time period of the pulse input using the current and previous counts.
process(Pulse_I)
begin
    if( rising_edge(Pulse_I) ) then
    --These different conditions eliminate the count overflow problem
    --which can happen once the module is run for a long time.
       if( Prev_Count < Curr_Count ) then
            DAT_O <= Curr_Count - Prev_Count;
            ERR_O <= '0';
        elsif( Prev_Count > Curr_Count ) then
        --X"F_F" is same as "1111_1111".
        --'_' is added for readability.
            DAT_O <= X"1_0000_0000_0000" - Prev_Count + Curr_Count;     
            ERR_O <= '0';
        else
         DAT_O <= (others => '0');
            ERR_O <= '1';  --Error bit is inserted here.
        end if;     
        Prev_Count <= Curr_Count;  --Re-setting the Prev_Count. 
    end if; 
end process;
end Behavioral;

CPLD VHDL频率计

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