Question

我正在设计使用unikgned比较器模块的有符号比较器。即，如果A和B是4位向量并且

if A[3] ==1 and B[3]==0 then 
  Gout = 0, Eout = 0 and Lout = 1.
if A[3]==0 and B[3]==1 then 
  Gout = 1, Eout = 0 and Lout = 0;
else if both A[3] and B[3] are same then 
  the unisigned comparator module has to be instantiated.

如何在if else语句中编写此门实例化？

module SCOMP(A,B,Great_in,Equal_in,Less_in,Great_out,Equal_out,Less_out);
  input[3:0] A;
  input[3:0] B;
  input Great_in,Equal_in,Less_in;
  output Great_out,Equal_out,Less_out;


  reg[3:0] X;
  reg[3:0] Y;
  reg p,q,r;
  wire x,y,z;
  initial
  begin
    X =  0000& A[2:0];
    Y =  0000& B[2:0];
  end

  COMP4 g1(X,Y,Gin,Ein,Lin,x,y,z);

  always @(*)
    begin
    if ((A[3]==0)&& (B[3]==1))
      begin
        assign p = 1;
        assign q = 0;
        assign r =0;
      end 
    else if ((A[3]== 1)&&(B[3]==0))
      begin
        assign p = 0;
        assign q = 0;
        assign r =  1;
      end 
    else 
      begin
        assign p = x;
        assign q = y;
        assign r = z;
      end
    end

  assign Great_out  = p;
  assign Equal_out = q;
  assign Less_out = r;

endmodule

Answer 1

Verilog是一种硬件描述语言。硬件存在或不存在。实例化就像将芯片焊接到PCB上一样。在if语句中实例化内容就像设计一个PCB，芯片可以根据PCB的一些输入神奇地出现或消失。

你的＆＃34;无符号比较器模块＆＃34;必须一直存在 - 必须无条件地实例化。然后，您需要使用if语句来决定是否使用此＆＃34;无符号比较器模块的输出＆＃34;或者忽略它们，例如：

// the instance of the "unsigned comparator module"
unsigned_comparator_module UCM ( ... .gout(ucm_gout), .eout(ucm_eout), .lout(ucm_lout) ... );

always @* begin
  if (A[3] == 1 && B[3] == 0) begin
    Gout = 0; Eout = 0; Lout = 1;
  end else if (A[3] == 0 && B[3] == 1) begin
    Gout = 1; Eout = 0; Lout = 0;
  end else if (A[3] == B[3]) begin
    Gout = ucm_gout; Eout = ucm_eout; Lout = ucm_lout;
  end
end

Answer 2

在if条件中执行此操作的最佳方法是将比较器代码写入您想要的位置。对于eaxample

AngularJS

在verilog中if else语句中的门实例化

2 个答案: