我写了这样的代码:
if (a) begin
//some coding
end
else begin
stage = 0;
if (b) begin
if (stage == 0) begin
stage = 1;
end
else if (stage == 1) begin
stage = 2;
end
else begin
stage = 0;
end
else
// some coding
end
end
当stage为1时,stage == 1内的代码无法执行。我的代码有什么问题吗?
答案 0 :(得分:1)
这样,它无法正常工作。 你必须把它放在一个过程中,即总是@(某事)。
//adding a signal needed
reg[1:0] stage_next;
always@(*)begin//Means that everytime an event occurs in one of the signals used in the following code,
//the code contained in this process will be executed
if (a) begin
//some coding
end
else begin
stage = 0;
if (b) begin
if (stage == 0) begin
//stage = 1;//this assignement will produce a combinatorial loop
//when the value of 'stage' changes the process(always@(*))
//will be re-executed. You have to assign another signal(stage_next here)
stage_next = 1
end
else if (stage == 1) begin
//stage = 2;//Same here
stage_next = 2;
end
else begin
//stage = 0;//Same here
stage_next = 0;
end
else
// some coding
end
end
end
//The other process where stage will take the value of stage_next should be synchronous
//It will break the combinatorial loop
always@(posedge clk)
stage <= stage_next;
答案 1 :(得分:0)
stage = 0
之前的阻止分配if (b)
在评估stage == 1
条件之前将阶段强制为零。
对所有<=
分配使用非阻止分配(stage
),您应该获得预期的行为。见How to interpret blocking vs non blocking assignments in Verilog?
您的代码块必须位于顺序块内(时钟触发,例如:always @(posedge clk)
)
答案 2 :(得分:0)
我说你的缩进是误导性的,请改为:
always @(*)
if (a) begin
//some coding
end
else begin
stage = 1;
if (b) begin
if (stage == 0) begin
stage = 1;
end
else if (stage == 1) begin
stage = 2;
end
else begin
stage = 0;
end
end // Your code did not have this end
else begin // This begin was also missing
// some coding
end
end
所以我想你是说如果你有那个代码,那你就不会看到舞台== 2 ??? 因为如果没有这些代码修改,你就会将else绑定到意外的if