Question

我正在尝试创建一个可以连接到VHDL字符串的SystemVerilog模块。但是，我在SystemVerilog中找不到相应的类型。使用type＆＃34; string＆＃34;导致Questa中的精化错误。

VHDL代码：

library IEEE;
use IEEE.std_logic_1164.all;

entity tb_serdes_support is    
end entity;

architecture beh of tb_serdes_support is    
    component serdes_support is port (    
        cmd         : in string    
    );
    end component;

    signal cmd  : string(1 to 100);

begin    
    i_srds_support: serdes_support port map (
        cmd         => cmd    
    );

    process
    begin    
        cmd(1 to 12) <= "hello world!";    
        wait for 10 ns;    
        cmd(1 to 18) <= "hello world again!";    
        wait;    
    end process;    

end architecture;

SV代码：

module serdes_support (cmd);

import uvm_pkg::*;

input string cmd;

always_comb begin    
    $display(cmd);    
end

endmodule

编辑：错误消息（Questa）：

**错误：（vsim-3059）无法将VHDL阵列信号连接到Verilog标量端口＆＃39; cmd＆＃39;。

Answer 1

VHDL中的string是固定大小的数组，而在SystemVerilog中，它是具有可变大小的单数类型。您可能需要将VHDL字符串转换为SystemVerilog中的字节数组。

Answer 2

您可以在适当的“位向量”中转换VHDL字符串，并在Verilog环境中使用此“位向量”。在Verilog中你可以解释它然后你想要的例如与％s。

mov_vhd.vhd：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY mod_vhd IS
    PORT
        (
            clk : IN std_ulogic;
            str_out : OUT string
        );
END ENTITY mod_vhd;

ARCHITECTURE sim OF mod_vhd IS

BEGIN

    clock_out_string: PROCESS IS


    BEGIN
        FOR i IN 0 TO 9 loop
            WAIT UNTIL rising_edge(clk);
            str_out <= "Hallo    "&integer'IMAGE(i);
        END LOOP;

    END PROCESS clock_out_string;

END ARCHITECTURE sim;

mod_ver.sv：

module mod_ver (
    input [79:0] my_string
);

initial begin
   forever @my_string
      $display ("see %s",my_string);
end


endmodule // mod_ver

top_vhd.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY top_vhd IS
END ENTITY top_vhd;

ARCHITECTURE sim OF top_vhd IS

SIGNAL clk: std_ulogic := '0';
SIGNAL str_out : string (1 TO 10);
SIGNAL str_out_ver : std_logic_vector (79 DOWNTO 0);

BEGIN

    clk <= NOT clk AFTER 10 ns;

    mod_vhd_i: ENTITY work.mod_vhd
        PORT MAP (
            clk     => clk,
            str_out => str_out
        );

    gen_vec: for i in str_out'range generate
        str_out_ver((11-i)*8-1 downto (11-i)*8-8) <= std_logic_vector(to_unsigned(character'pos(str_out(i)), 8));
    end generate;    

    mod_ver_i: ENTITY work.mod_ver
        PORT MAP (
            my_string => str_out_ver
        );


END ARCHITECTURE sim;

哪个SystemVerilog构造对应VHDL字符串？

2 个答案: