Question

我有一个相当大的项目，由许多模块组成，这些模块集成在一个顶级组件中。我已经为这些模块创建了测试平台，这些模块使用了API包（我和它们一起创建）。我还有一个顶级测试平台，可以对集成系统进行整体测试。

对于其中一个组件，我有兴趣在其MyModuleAPIPackage中使用VHDL-2008层次结构名称，以便从顶级测试平台访问内部信号。因为我正在尝试编写模块化和可重用的代码，所以我希望能够实例化包，以便它在组件级测试中引用模块的信号（模块位于顶层）

<<signal .MyComponent.MySignal : std_logic>>

并且也在顶级测试中（有底层结构）

<<signal .MySystem.MySubSystem.MyComponent.MySignal : std_logic>>

也许这可以通过分层名称和泛型的组合来实现？

这是一些（伪）代码，举例说明了我想要实现的目标。

MyModule.vhd

-- MyModule.vhd
entity MyModule is
  port(
    CLK : in std_logic;
    RST : in std_logic;

    DATA_IN : in std_logic_vector(7 downto 0);
    DATA_OUT : out std_logic_vector(7 downto 0)
  );
end entity MyModule;

architecture behavioral of MyModule is
  -- Signal and constant definitions here.
begin
  -- Describes how MyModule behaves.
end architecture behavioral;

----------------------
-- MyModule Test-Bench
----------------------
entity MyModule_tb is
end entity MyModule_tb;

architecture test of MyModule_tb is
  -- Signal and constant definitions here
  signal CLK, RST : std_logic := '0';
  signal DATA_IN, DATA_OUT : std_logic_vector(7 downto 0) := (others = '0');

  procedure DoComplexStuff(
    InstructionCode : natural
  )
  is
  begin
    case InstructionCode is
      when 0 =>
        DATA_IN <= "01010101";
        wait until CLK = '1';
        DATA_IN <= "00110011";
        wait until CLK = '1';
        -- Lots of pretty complex stimuli
        assert DATA_OUT = "00110011"
        report "Output mismatch!"
        severity failure;
      when 1 =>
        -- Lots of pretty complex stimuli
      -- when ... =>
      -- Plenty more instruction codes
      others =>
        null;
  end procedure DoComplexStuff;  
begin
  CLK <= not CLK after 1 ms;

  MainTestProc:
  process
  begin
    for i in 0 to 99 loop
      DoComplexStuff(i);
    end loop;
  end;

  DUT: entity work.MyModule(behavioral)
    port map(
      CLK => CLK,
      RST => RST,
      DATA_IN => DATA_IN,
      DATA_OUT => DATA_OUT
    );
end architecture test;

我希望procedure DoComplexStuff可以在顶层获得。

MyModuleApi.vhd

package MyModuleAPI is
  generic(
  -- Programatically defined aliases
    PATH : path;
  )
  alias CLK is <<signal PATH.CLK : std_logic);
  alias RST is <<signal PATH.RST : std_logic);
  alias DATA_IN is <<signal PATH.DATA_IN : std_logic_vector(7 downto 0));
  alias DATA_OUTis <<signal PATH.DATA_OUT : std_logic_vector(7 downto 0));

  procedure DoComplexStuff(
    InstructionCode : in natural
  );
end package;

package body MyModuleAPI is
  -- I can now include this package within MyModule_tb and
  -- MyTopLevelComponent_tb and call DoComplexStuff to interact with the signals
  -- from MyModule
  procedure DoComplexStuff(
    InstructionCode : natural
  )
  is
  begin
    case InstructionCode is
      when 0 =>
        DATA_IN <= "01010101";
        wait until CLK = '1';
        DATA_IN <= "00110011";
        wait until CLK = '1';
        -- Lots of pretty complex stimuli
        assert DATA_OUT = "00110011"
        report "Output mismatch!"
        severity failure;
      when 1 =>
        -- Lots of pretty complex stimuli
      -- when ... =>
      -- Plenty more instruction codes
      others =>
        null;
  end procedure DoComplexStuff;
end package body MyModuleAPI;

因此，MyModule_tb将包含MyModuleAPI包，其中一个参数将自己指定为顶级组件，而MyTopLevel_tb将包含相同的包，其参数正确指定了MyModule的路径。（？）

注意：是的，我打算在顶级测试期间修改（bit-bang）内部信号。这与使用ModelSim的“signal_force”和“signal_release”命令类似。

提前感谢您的指导！

是否可以在VHDL 2008中以编程方式定义分层名称？

MyModule.vhd

MyModuleApi.vhd

0 个答案: