VHDL上不需要的IN端口和OUT端口

时间:2017-06-21 06:14:40

标签: port vhdl quartus

我有两个用VHDL编写的实体,我使用Quartus在ALTERA FPGA上运行它们。 它们中的每一个都使用了大约15%的FPGA资源,但是当我一起使用它们时,使用的资源将超过100%。

--==========Library===========
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.numeric_std.all;
use IEEE.std_logic_signed.all;
use ieee.std_logic_arith.all;

entity Sobel is
port(
    SobelP          : out std_logic_vector(11 downto 0);
--  oM11, oM12, oM13, oM21, oM22, oM23, oM31, oM32, oM33  : inout std_logic_vector(11 downto 0);
    iGray : in std_logic_vector(11 downto 0);
    iX_Cont,    iY_Cont : in std_logic_vector(15 downto 0);
    iDVAL, iCLK, iRST   : in std_logic
    );
end Sobel;


architecture behv of Sobel is

    COMPONENT Sobel_Operator is
        port(
        G   : out std_logic_vector(11 downto 0);
        iM11, iM12, iM13, iM21, iM22, iM23, iM31, iM32, iM33  : in std_logic_vector(11 downto 0);
        iDVAL, iCLK, iRST   : in std_logic
        );
    END COMPONENT;

TYPE register_file IS ARRAY ( 0 TO 639 ) OF STD_LOGIC_VECTOR( 11 DOWNTO 0 );

    SIGNAL xCount, yCount           : std_logic_vector(15 downto 0);

    SIGNAL oM11, oM12, oM13, oM21, oM22, oM23, oM31, oM32, oM33  : std_logic_vector(11 downto 0) := (11 downto 0 => '0');


    SIGNAL Line2                        : register_file;
    SIGNAL Line3                        : register_file;

    SIGNAL P                          : std_logic_vector(11 downto 0);  


BEGIN

    Sobel_OP : Sobel_Operator
        PORT MAP(P, oM11, oM12, oM13, oM21, oM22, oM23, oM31, oM32, oM33, iDVAL, iCLK, iRST);

PROCESS (iCLK, iRST)

    constant size : integer := 639;

BEGIN

if ( rising_edge(iCLK)) then


    if(iRST = '0') then
        for i in 0 to size LOOP
            Line2(i) <= (others => '0');
            Line3(i) <= (others => '0');
        end LOOP;

    elsif (iDVAL = '1') then

        oM33 <= oM32;
        oM32 <= oM31;
        oM31 <= Line3(0);
        oM23 <= oM22;
        oM22 <= oM21;
        oM21 <= Line2(0);
        oM13 <= oM12;
        oM12 <= oM11;
        oM11 <= iGray;

        for i in 1 to size LOOP
            Line2(i-1)<= Line2(i);
            Line3(i-1)<= Line3(i);
        end loop;
        Line2(size) <= oM11;
        Line3(size) <= oM21;


        SobelP <= P;
    end if;
end if;


END PROCESS;

END behv;

AND

--==========Library===========
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_signed.all;
use ieee.std_logic_arith.all;

entity Sobel_Operator is
port(
    G   : out std_logic_vector(11 downto 0);
    iM11, iM12, iM13, iM21, iM22, iM23, iM31, iM32, iM33  : in std_logic_vector(11 downto 0);
    iDVAL, iCLK, iRST   : in std_logic
    );
end Sobel_Operator;


architecture behv of Sobel_Operator is


BEGIN


PROCESS (iCLK, iRST)
variable I11, I12, I13, I21, I22, I23, I31, I32, I33, S, Gx, Gy     : integer := 0;

BEGIN


    if(rising_edge(iCLK)) then

        I11 := CONV_INTEGER((iM11));
        I12 := CONV_INTEGER((iM12));
        I13 := CONV_INTEGER((iM13));
        I21 := CONV_INTEGER((iM21));
        I22 := CONV_INTEGER((iM22));
        I23 := CONV_INTEGER((iM23));
        I31 := CONV_INTEGER((iM31));
        I32 := CONV_INTEGER((iM32));
        I33 := CONV_INTEGER((iM33));

        Gx := I11-I13+2*I21-2*I23+I31-I33;
        Gy := -I11-2*I12-I13+I31+I32+I33;
        IF (Gx > 0) THEN
            Gx := Gx;
        ELSE
            Gx := Gx*(-1);
        END IF;

        IF (Gy > 0) THEN 
            Gy := Gy;
        ELSE
            Gy := Gy*(-1);
        END IF;


        S := Gx+Gy;

        G <= std_logic_vector(to_unsigned(S, G'length));
    end if;
END PROCESS;

END behv;

当我查看RTL时,我可以看到第一个代码中的所有register_files作为输入/输出,我无法找到原因

由于

0 个答案:

没有答案