Question

我使用verilog创建一个ALU！所以我写了一些代码和模块：

module full_adder ( A, B, Cin ,S, Cout);
output S, Cout;
input A, B, Cin;
assign {Cout, S} = A + B + Cin;
endmodule

//---------

module adder2bit (A,B,Cin,S,cout);
input [1:0]A,B;
input Cin;
output [1:0]S;
output cout;
wire c;
fulladder I0 (A[0],B[0],Cin,S[0],c);
fulladder I1 (A[1],B[1],c,S[1],cout);
endmodule

//----------
module adder3bit (A,B,Cin,S,cout);
input [2:0]A,B;
input Cin;
output [2:0]S;
output cout;
wire [1:0]c;
fulladder I0 (A[0],B[0],Cin,S[0],c[0]);
fulladder I1 (A[1],B[1],c[0],S[1],c[1]);
fulladder I2 (A[2],B[2],c[1],S[2],cout);
endmodule
//----------

//----------
module mux2to1 (A,B,select,Sout,Cout);

    input [2:0] A,B;
    output [1:0]Sout;
    output Cout;
    reg [1:0]Sout;
    reg Cout;
    input select;
    always @( * )begin
    case (select)
    0: Sout <= A[1:0];
    1: Sout <= B[1:0];
    endcase
    Cout=select?B[2]:A[2]; 
    end   
endmodule

//---------?

module twothComplement (in,out);


  input [7:0] in;
  output [7:0] out;
  integer flag;
  integer i;
  reg [7:0]out;
  always @ (*)begin
  flag = 0;  
  for(i=0;i<8;i=i+1)
  begin
    out[i] =0;
    if (flag == 1) begin
      if (in[i] == 0)begin
        out[i] = 1;
      end
      else begin
        out[i] = 0;
      end  
    end    
    else if (in[i] == 1) begin
      flag = 1;
      out[i] = 1;
    end

  end
               end  

endmodule





//----------

module triple_left_Shift(p,q);
  input [7:0]p;
  output  [7:0]q;
  assign q[3]=p[0];
  assign q[4]=p[1];
  assign q[5]=p[2];
  assign q[6]=p[3];
  assign q[7]=p[4];
  assign q[0]=p[5];
  assign q[1]=p[6];
  assign q[2]=p[7];
endmodule


module triple_right_Shift(p,q);
  input [7:0]p;
  output  [7:0]q;
  assign q[0]=p[3];
  assign q[1]=p[4];
  assign q[2]=p[5];
  assign q[3]=p[6];
  assign q[4]=p[7];
  assign q[5]=p[0];
  assign q[6]=p[1];
  assign q[7]=p[2];
endmodule

//----------
module XO (A,B,Cout);   
  input [7:0]A,B;
  output [7:0]Cout;
  reg [7:0]Cout;
  integer i;
  always @(*)begin
  for( i=0 ; i<8 ; i=i+1) begin
    if (i < 4)begin
      Cout[i] = A[i] & B[i];
    end  
    if (i >= 4)begin
      Cout[i] = A[i] | B[i];
    end   
  end
  end
endmodule
//----------
module Add(A,B,Sum,cout);
 input [7:0] A,B;
 wire [8:0] fullSum;
 output [7:0] Sum;
 output cout;
 wire [8:0]x,y;
 assign x = { A[7] , A}; 
 assign y = { B[7] , B}; 


 wire [1:0]s1,s2,s3,s4,s5,s6;
 wire c1,c2,c3,c4,c5,c6,ca,cb,cc,cd;

 adder3bit I1(x[2:0],y[2:0],1'b0,fullSum[2:0],ca);

 adder2bit I2(x[4:3],y[4:3],1'b0,s1,c1);
 adder2bit I3(x[4:3],y[4:3],1'b1,s2,c2);
 mux2to1 I4({c1,s1},{c2,s2},ca,fullSum[4:3],cb);

 adder2bit I5(x[6:5],y[6:5],1'b0,s3,c3);
 adder2bit I6(x[6:5],y[6:5],1'b1,s4,c4);
 mux2to1 I7({c3,s3},{c4,s4},cb,fullSum[6:5],cc);

 adder2bit I8(x[8:7],y[8:7],1'b0,s5,c5);
 adder2bit I9(x[8:7],y[8:7],1'b1,s6,c6);
 mux2to1 I10({c5,s5},{c6,s6},cc,fullSum[8:7],cd);

 assign cout = fullSum[8];
 assign Sum = fullSum[7:0];
endmodule 

//----------
module Sub(A,B,Sub,cout);
 input [7:0] A,B;
 output [7:0] Sub;
 output cout;
 wire [7:0] tB;

 twothComplement I1 (B,tB);
 Add I2 (A,tB,Sub,cout);
 assign cout = 1'bx;
endmodule 

//----------
module ALU(A,B,Selector,s,Carry);
    input [7:0] A,B;
    input [2:0] Selector;
    output reg Carry;
    output reg [7:0]s;
    wire [7:0]w[4:0];
    wire [1:0]c;

    Add I0(A,B,w[0],c[0]);
    Sub I1(A,B,w[1],c[1]); 
    triple_right_Shift I2(A,w[2]);
    triple_left_Shift I3(A,w[3]);
    XO I4(A,B,w[4]);

    always @( A,B,Selector )begin
        case (Selector)
            3'b000:  begin s<=w[0]; Carry=c[0]; end
            3'b001:  begin s<=w[1]; Carry=c[1]; end
            3'b010:   s<=w[2];
            3'b011:   s<=w[3];
            3'b100:   s<=w[4];
            default: s = 8'b00000000;
        endcase
        end
endmodule

这段代码编译得非常好，也可以模拟。但是当我想要测试ALU模块和初始A＆amp; B $ Selector，第一波（第一次运行）不起作用。改变后选择它的工作！请帮我这个

ALU不在第一波工作（verilog）

0 个答案: