什么是Xilinx Vivado中的模拟器45-1错误？

Question

我一直在尝试制作通用序列检测器。当我尝试模拟我的设计时，我得到一个模拟器45-1致命运行时错误。有人可以帮我这个。这是我的测试台和设计。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Sequence_tb is
end Sequence_tb;

architecture Behavioral of Sequence_tb is
    component sequence is
        Generic(width: integer;
                sequence: std_logic_vector);
        Port(din,CLK,RST:in std_logic;
             dout: out std_logic;
             temp: buffer std_logic_vector(0 to width-1));
    end component;
    constant CLK_period: time := 10ns;
    constant width: integer := 4;
    constant sequence0: std_logic_vector(width-1 downto 0) := "1010";
    signal din,CLK,RST,dout: std_logic := '0';
    signal temp : std_logic_vector(0 to width-1) := (others=>'0');
begin
    uut: sequence generic map(width=>width,sequence=>sequence0)
                  port     map(din=>din,CLK=>CLK,RST=>RST,dout=>dout,temp=>temp);

    CLK_proc: process
    begin
        CLK <= not CLK;
        wait for CLK_period;
    end process;

    RST_proc: process
    begin
        RST <= '1';
        wait for 20 ns;
        RST <= '0';
        wait;
    end process;

    din_proc: process
    begin
        din <= '1';
        wait for 30 ns;
        din <= '0';
        wait for 10 ns;
        din <= '1';
        wait for 10 ns;
        din <= '0';
        wait for 10 ns;
        din <= '1';
        wait for 10 ns;
        wait;
    end process;
end Behavioral; 

设计文件：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Sequence is
    Generic(width: integer;
            sequence: std_logic_vector);
    Port (din, CLK, rst: in std_logic;
          dout: out std_logic;
          temp: buffer std_logic_vector(0 to width-1));
end Sequence;

architecture Beh of Sequence is
    subtype statetype is integer range 0 to width-1;
    signal prstate,nxstate: statetype := 0;
begin
    process(RST,CLK)
    begin
        if RST='1' then
            temp <= (others => '0');
            nxstate <= 0;
        elsif CLK'event and CLK='1' then
            temp(prstate) <= din;
            for k in prstate downto 0 loop
                if temp(k downto 0) = sequence(k downto 0) then
                    nxstate <= k;
                    exit;
                else temp <= temp(1 to width-1) & '0';
                end if;
            end loop;
        end if;
        prstate <= nxstate;
    end process;
    dout <= '1' when prstate = width-1 and din = sequence(sequence'left) else '0';
end Beh;