输入变为零后如何保持相同的FSM状态? (SystemVerilog的)

时间:2017-05-07 17:12:18

标签: system-verilog led fsm

我正在尝试制作一个FSM,根据按下的按钮打开LED矩阵上的不同LED。但是,LED不会保持打开状态,释放按钮后,第一个LED会再次亮起。 这是代码:

module OneLed( input logic clk, reset, input logic [1:0] button, 
           output logic [7:0] rows, 
           output logic shcp, stcp, mr, oe, ds); //The LED matrix has 3 74hc595 shift registers below it

      logic [7:0] [23:0] in;
      logic [1:0] butreg; // thought a register would remember the button input
      assign butreg = button; 

      //FSM
      typedef enum logic [1:0] {S0, S1, S2} statetype;
      statetype state , nextstate;

     //state register
     always_ff @(posedge clk, posedge reset)
           if (reset) state <= S0;
           else state <= nextstate;

     //next state logic 
           always_comb
                 case(butreg)
                     S0: if (2'b01) nextstate = S1;
                         else if (2'b10) nextstate = S2;
                         else nextstate = S0;

                     S1: if (2'b01) nextstate = S2;
                         else if (2'b10) nextstate = S0;
                         else nextstate = S1;

                     S2: if (2'b01) nextstate = S0;
                         else if (2'b10) nextstate = S1;
                         else nextstate = S2;     
                     default: nextstate = S0;
           endcase 

    //output logic 
    always_comb
           begin
               if (state == S0)
                  in [0] = 24'b10000000_00000000_00000000;
               else if (state == S1)
                  in [0] = 24'b00000000_10000000_00000000;
               else  if (state == S2)        
                  in[0] =  24'b00000000_00000000_10000000;
   end         

   led LED ( clk, in , rows, shcp, stcp, mr, oe, ds); // this module works fine
endmodule   

1 个答案:

答案 0 :(得分:0)

assign butreg = button; 

此声明将 butreg 视为电线,直接连接到输入信号按钮

如果您想将按钮的值锁定到 butreg 寄存器中,则需要使用始终块并触发适当的事件(posedge clk或*或其他一些条件。

例如,您可以使用

代替上述分配
always @(posedge clk) begin
  if (button == 2'b00) begin
    butreg <= butreg;
  end
  else begin
    butreg <= button;
  end
end