我的VHDL设计需要帮助。如果有人在外面看看，我会很感激。几天后我没有找到错误的观点。
设计的目的： 我有一个有限状态机（FSM2），并希望多次处理它（现在2次）。因此，我想使用另一个有限的st。马赫。 （FSM1）。但是FSM不是必需的。我希望它们工作的条件如下所述。
提前致谢。
flag0 = 1启动FSM1
FSM1生成flag1 = 1，启动另一个过程以生成确定宽度脉冲（P）以启动FSM2。在flag2之前P = 0，并且重置flag1 = 0。
FSM2在操作期间生成flag2 = 1。最后它回到flag2 = 0 flag2 = 0将FSM1 ST1的状态改为ST2，flag1 = 1，FSM2再次通过P，flag2 = 0再次处理
FSM1返回ST0 flag1 = 0
没有FSM1整个设计过程正确。
flag0和flag 2没问题，但是标志1驱动不正确！
FSM1：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE IEEE.NUMERIC_STD.ALL;
entity Data_Organiser is
Port ( clk : IN STD_LOGIC ;
DO_Period_Flag : IN STD_LOGIC ;
DO_Data_Sent_progress_flag : IN STD_LOGIC ;
DO_DATA : IN STD_LOGIC_VECTOR (15 downto 0) ;
DO_Data_Part : OUT STD_LOGIC_VECTOR (7 downto 0) ;
DO_Set_flag : OUT STD_LOGIC ;
state_info : out std_logic_VECTOR(3 DOWNTO 0) );
end Data_Organiser;
architecture Behavioral of Data_Organiser is
type STATES is (ST_IDLE, ST_FIRST_PART, ST_SECOND_PART, ST_CLEANUP);
signal NEXT_STATE : STATES := ST_IDLE;
signal s_clk : STD_LOGIC ;
signal s_DO_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0) ;
signal s_DO_Data_Part : STD_LOGIC_VECTOR( 7 DOWNTO 0) ;
signal s_DO_Period_Flag : STD_LOGIC ;
signal s_DO_Data_Sent_progress_flag : STD_LOGIC ;
signal s_DO_Set_flag : STD_LOGIC ;
begin
s_clk <= clk ;
s_DO_Period_Flag <= DO_Period_Flag ;
s_DO_Data_Sent_progress_flag <= DO_Data_Sent_progress_flag ;
s_DO_DATA <= DO_DATA ;
FSM_SERIAL : process (s_clk, s_DO_DATA,s_DO_Period_Flag,s_DO_Data_Sent_progress_flag)
begin
if (rising_edge(s_clk)) then
case NEXT_STATE is
when ST_IDLE =>
if ( s_DO_Period_Flag = '1' ) AND ( s_DO_Data_Sent_progress_flag = '0' ) then
NEXT_STATE <= ST_FIRST_PART ;
else
NEXT_STATE <= ST_IDLE ;
s_DO_Set_flag <= '0' ;
end if ;
when ST_FIRST_PART =>
s_DO_Data_Part <= "01110111";
s_DO_Set_flag <= '1' ;
if ( s_DO_Period_Flag = '0' ) AND ( s_DO_Data_Sent_progress_flag = '0' ) then
NEXT_STATE <= ST_SECOND_PART ;
else
s_DO_Set_flag <= '0' ;
NEXT_STATE <= ST_FIRST_PART ;
end if ;
when ST_SECOND_PART =>
s_DO_Data_Part <= "01000100" ;
s_DO_Set_flag <= '1' ;
if ( s_DO_Data_Sent_progress_flag = '0' ) then
NEXT_STATE <= ST_CLEANUP ;
else
s_DO_Set_flag <= '0' ;
NEXT_STATE <= ST_SECOND_PART ;
end if ;
when ST_CLEANUP =>
s_DO_Data_Part <= X"00";
NEXT_STATE <= ST_IDLE ;
when others =>
s_DO_Set_flag <= '0' ;
NEXT_STATE <= ST_IDLE ;
end case;
end if;
end process FSM_SERIAL ;
DO_Data_Part <= s_DO_Data_Part ;
DO_Set_flag <= s_DO_Set_flag ;
end Behavioral;
FSM2：
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL ;
entity Serial_Link is
generic(Baud_Match_Num : integer := 1085 );
port ( clk : IN STD_LOGIC ; -- 125 MHz
SL_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
SL_DATA_REQUEST : IN STD_LOGIC ;
SL_START_BIT : OUT STD_LOGIC ;
SL_DATA_SERIAL : OUT STD_LOGIC ;
SL_STOP_BIT : OUT STD_LOGIC ;
SL_DATA_SENT_PROGRESS_FLAG : OUT STD_LOGIC);
end Serial_Link;
architecture Behavioral of Serial_Link is
signal s_clk : STD_LOGIC;
type STATES is (ST_IDLE, ST_START_BIT, ST_DATA_BITS, ST_STOP_BIT, ST_CLEANUP);
signal NEXT_STATE : STATES := ST_IDLE;
signal Bit_Keep_Count : integer range 0 to Baud_Match_Num-1 := 0;
signal Bit_index : integer range 0 to 7 := 0; -- 8 Bits Total
signal s_SL_DATA : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
s_clk <= clk ;
FSM_SERIAL : process (s_clk,SL_DATA)
begin
if (rising_edge(s_clk)) then
case NEXT_STATE is -- TRANSMISSION STARTS IN " IDLE " MODE
when ST_IDLE =>
SL_START_BIT <= '1';
SL_DATA_SERIAL <= '1';
SL_STOP_BIT <= '0';
Bit_Keep_Count <= 0 ;
Bit_index <= 0 ;
if SL_DATA_REQUEST = '1' then
s_SL_DATA <= SL_DATA;
NEXT_STATE <= ST_START_BIT;
SL_DATA_SENT_PROGRESS_FLAG <= '1' ; -- DATA SENDING STARTED : FLAG --> 1
else
NEXT_STATE <= ST_IDLE;
SL_DATA_SENT_PROGRESS_FLAG <= '0' ; -- DATA SENDING NOT STARTED : FLAG --> 0
end if;
when ST_START_BIT =>
SL_DATA_SERIAL <= '0'; -- START BIT IN SERIAL DATA !!!
if Bit_Keep_Count < Baud_Match_Num-1 then
Bit_Keep_Count <= Bit_Keep_Count + 1;
NEXT_STATE <= ST_START_BIT;
SL_START_BIT <= '0';
else
Bit_Keep_Count <= 0;
NEXT_STATE <= ST_DATA_BITS;
SL_START_BIT <= '1';
end if;
when ST_DATA_BITS =>
SL_DATA_SERIAL <= s_SL_DATA(Bit_index);
if Bit_Keep_Count < Baud_Match_Num-1 then
Bit_Keep_Count <= Bit_Keep_Count + 1 ;
NEXT_STATE <= ST_DATA_BITS ;
else
Bit_Keep_Count <= 0 ;
if Bit_index < 7 then
Bit_index <= Bit_index + 1;
NEXT_STATE <= ST_DATA_BITS ;
else
Bit_index <= 0 ;
NEXT_STATE <= ST_STOP_BIT ;
end if;
end if;
when ST_STOP_BIT =>
SL_DATA_SERIAL <= '1' ; -- STOP BIT IN SERIAL DATA
if Bit_Keep_Count < Baud_Match_Num-1 then
Bit_Keep_Count <= Bit_Keep_Count + 1 ;
NEXT_STATE <= ST_STOP_BIT ;
SL_STOP_BIT <= '1';
else
Bit_Keep_Count <= 0 ;
NEXT_STATE <= ST_CLEANUP ;
SL_STOP_BIT <= '0' ;
end if;
when ST_CLEANUP =>
SL_DATA_SENT_PROGRESS_FLAG <= '0' ; -- DATA SENDING FINISHED: FLAG --> 0
NEXT_STATE <= ST_IDLE ;
when others =>
NEXT_STATE <= ST_IDLE ;
end case;
end if;
end process FSM_SERIAL ;
end Behavioral ;