通过输入生成分量或驱动信号

时间:2017-05-01 09:13:22

标签: vhdl

我正在尝试创建一个具有以下行为的架构:

entity component1 is
    generic (
        debounce_ticks          : natural range 0 to natural'high
    );
    port (
        rst                     : in    STD_LOGIC;
        clk                     : in    STD_LOGIC;
        sclk                    : in    STD_LOGIC;
        [...]              
    );
end component1;
architecture Behavioral of component1 is
     signal sclk_debounced       : STD_LOGIC;
[...]
begin
debouncer:
    if debounce_ticks > 0 generate
        sclk_debouncer : entity work.static_debouncer
        generic map (
            debounce_ticks => debounce_ticks
        )
        port map (
            clk => clk,
            pulse_in => sclk,
            pulse_out => sclk_debounced
        );
    else --Or something
       sclk_debounced <= sclk
    end generate debouncer;
[..]
end Behavioral;

所以,我有这个信号,我想要根据通用信息连接到一个组件的输入或循环。

我怎样才能做到这一点?

2 个答案:

答案 0 :(得分:1)

if generate语句不支持else子句,因此您需要反转检查以模拟else。另外,您需要为另一个if generate添加第二个标签。

begin
debouncer:
    if debounce_ticks > 0 generate
        sclk_debouncer : entity work.static_debouncer
        generic map (
            debounce_ticks => debounce_ticks
        )
        port map (
            clk => clk,
            pulse_in => sclk,
            pulse_out => sclk_debounced
        );
    end generate debouncer;
no_debouncer:
    if debounce_ticks <= 0 generate
       sclk_debounced <= sclk
    end generate no_debouncer;
[...]

答案 1 :(得分:0)

您需要进行两项更改:

  1. component是保留字,不能用作标识符。
  2. generate
  3. 之后缺少保留字else

    重命名实体:

    entity component1 is
      generic (
        debounce_ticks          : natural range 0 to natural'high
      );
      port (
        rst                     : in    STD_LOGIC;
        clk                     : in    STD_LOGIC;
        sclk                    : in    STD_LOGIC;
        -- [...]              
      );
    end entity component1;
    

    修正生成声明:

    architecture Behavioral of component1 is
      signal sclk_debounced       : STD_LOGIC;
      -- [...]
    begin
      debouncer: if debounce_ticks > 0 generate
        sclk_debouncer : entity work.static_debouncer
          generic map (
            debounce_ticks => debounce_ticks
          )
          port map (
            clk => clk,
            pulse_in => sclk,
            pulse_out => sclk_debounced
          );
      else generate --Or something
        sclk_debounced <= sclk
      end generate debouncer;
      -- [..]
    end architecture Behavioral;