Question

我有一个非常基本的问题。我有一个时钟，一个计数器和一个信号，指示在FPGA的最终实现中路由到输出的另外两个信号应该改变。

我的问题是，当我模拟以下测试平台时，cs_a_o和cs_g_o会被驱动到＆＃39; X＆＃39;而不是＆＃39; 0＆＃39;。当问题出现时，我在几个地方驱动信号，但我无法看到代码如何更简单，因为它必须在进程中（最终实现将处理串行通信）

在我努力解决问题的过程中，我发出了一个新的信号can，它与cs_X_o同时发生了同样的事情 - 除了它不是在端口映射中，因为它是一个内部信号。我不明白为什么一个信号按预期运行，而另外两个信号不是，即使它们在代码中受到相同的操作。

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS 
    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT test
    PORT(
         clk : IN  std_logic;
         CS_A_O : out  std_logic;
         CS_G_O : out  std_logic
         );
    END COMPONENT;

   --Inputs
   signal clk : std_logic := '0';

    --Outputs
    signal counter : integer range 0 to 125000 := 0;
    signal counter_next : integer range 0 to 125000 := 0;
    signal CS_A_O : std_logic := '1';
    signal CS_G_O : std_logic := '1';
    signal cs : std_logic := '1';
    signal can : std_logic := '1';
   -- Clock period definitions
   constant clk_period : time := 20 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: test PORT MAP (
          clk => clk,
          CS_A_O => CS_A_O,
          CS_G_O => CS_G_O
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
    end process;

    counter_process : process (clk) begin
        if (rising_edge(clk)) then
            counter <= counter_next;
            counter_next <= counter_next + 1;
            if (counter = 199) then
                counter <= 0;
                counter_next <= 1;
                cs <= not cs;
            end if;
        end if;
    end process;

    switching : process(clk) begin
        if (rising_edge(clk)) then
            if cs = '1' and can = '1' then
                can <= not can; -- this does as expected
                cs_a_o <= not cs_a_o; -- this doesn't work
            elsif cs = '0' and can = '0' then
                can <= not can; -- this does as expected
                cs_g_o <= not cs_g_o; -- this doesn't work
            end if;
        end if;
    end process;

    ASSERT ((CS_A_O = '1' or CS_A_O = '0')
    and (CS_G_O = '1' or CS_G_O = '0'))
        report "It's dead wrong. CS_A_O = " & std_logic'image(CS_A_O) &
        "  CS_G_O = " & std_logic'image(CS_G_O)
        severity error;
END;

Answer 1

cs_a_o和cs_g_o有两个驱动程序。首先是组件test的实例化，标签为uut。然后是您的流程switching。

尝试发表评论uut：

 -- Instantiate the Unit Under Test (UUT)
 -- uut: test PORT MAP (
 --        clk => clk,
 --        CS_A_O => CS_A_O,
 --        CS_G_O => CS_G_O
 --      );

任何分配信号的并发语句都会创建一个驱动程序。已解决类型的所有驱动程序的值有助于实现有效值。在包体std_logic_1164中，您可以找到std_logic的分辨率表和分辨率函数。

无法将信号驱动到＆＃39; 1＆＃39;或者＆＃39; 0＆＃39; 0

1 个答案: