Question

我有一个用d-flip触发器和多路复用器制作的移位器编写的vhdl代码，它运行并检查成功的语法。但是，现在我正在使用测试平台，我遇到了一些错误。

VHDL代码是：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX41 IS
 PORT (i3, i2, i1, i0 : IN BIT;
 s: IN BIT_VECTOR(1 DOWNTO 0);
 o: OUT BIT);
END MUX41;
ARCHITECTURE arch_mux41 OF MUX41 IS
BEGIN
 PROCESS(i3, i2, i1, i0, s)
 BEGIN
 CASE s IS
 WHEN "00" => o <= i0;
 WHEN "01" => o <= i1;
 WHEN "10" => o <= i2;
 WHEN "11" => o <= i3;
 WHEN OTHERS => NULL;
 END CASE;
 END PROCESS;
END arch_mux41;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DFF IS
 PORT(d, clk : IN BIT;
 q, qb : OUT BIT);
END DFF;
ARCHITECTURE arch_dff OF DFF IS
BEGIN
 PROCESS(clk)
 VARIABLE q_temp : BIT;
 BEGIN
 IF(clk'EVENT AND clk='1')THEN
 q_temp := d;
 END IF;
 q <= q_temp;
 qb <= NOT q_temp;
 END PROCESS;
END arch_dff; 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY UShift IS
 PORT(clk, il, ir : IN BIT;
 s: IN BIT_VECTOR(1 DOWNTO 0);
 i : IN BIT_VECTOR(3 DOWNTO 0);
 q : OUT BIT_VECTOR(3 DOWNTO 0));
END UShift;

ARCHITECTURE struct OF UShift IS

COMPONENT MUX41
 PORT (i3, i2, i1, i0 : IN BIT;
 s: IN BIT_VECTOR(1 DOWNTO 0);
 o: OUT BIT);
END COMPONENT;

COMPONENT DFF
 PORT(d, clk : IN BIT;
 q, qb : OUT BIT);
END COMPONENT;

FOR U1, U2, U3, U4: MUX41 USE ENTITY WORK.MUX41(arch_mux41);
FOR U5, U6, U7, U8: DFF USE ENTITY WORK.DFF(arch_dff);
 SIGNAL o: BIT_VECTOR(3 DOWNTO 0);
 SIGNAL qb: BIT_VECTOR(3 DOWNTO 0);
 SIGNAL qt:BIT_VECTOR(3 DOWNTO 0);
BEGIN
 U1:MUX41 PORT MAP(il,qt(2), i(3), qt(3), s, o(3));
 U2:MUX41 PORT MAP(qt(3), qt(1), i(2), qt(2), s, o(2));
 U3:MUX41 PORT MAP(qt(2), qt(0), i(1), qt(1), s, o(1));
 U4:MUX41 PORT MAP(qt(1), ir, i(0), qt(0), s, o(0));
 U5:DFF PORT MAP(o(3), clk, qt(3), qb(3));
 U6:DFF PORT MAP(o(2), clk, qt(2), qb(2));
 U7:DFF PORT MAP(o(1), clk, qt(1), qb(1));
 U8:DFF PORT MAP(o(0), clk, qt(0), qb(0));
 q <= qt;
END struct;

仅在检查测试平台中的语法时才会显示出现的错误消息。他们声明该实体与＆＃34; clk＆＃34;，＆＃34; il＆＃34;，＆＃34; ir＆＃34;，＆＃34; i＆＃34;，＆＃34的组件端口不匹配; s＆＃34;和＆＃34; q＆＃34;。有没有人对我可能有什么错误有任何想法？我已经在线阅读了类似问题的一些建议，但没有一个实际应用于此特定代码。

测试平台是：

LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY UShift_test IS
END UShift_test;

ARCHITECTURE behavior OF UShift_test IS 
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT UShift
    PORT(clk : IN  std_logic; il : IN  std_logic; ir : IN  std_logic; i : IN  std_logic_vector(3 downto 0); s:IN std_logic_vector(1 downto 0); 
    q : OUT  std_logic_vector(3 downto 0));
    END COMPONENT;

   --Inputs
   signal clk : std_logic := '0';
   signal il : std_logic := '0';
   signal ir : std_logic := '0';
   signal s : std_logic_vector(1 downto 0) := (others => '0');
   signal i : std_logic_vector(3 downto 0) := (others => '0');

    --Outputs
   signal q : std_logic_vector(3 downto 0);
   -- Clock period definitions
   constant clk_period : time := 20 ns;

BEGIN 
    -- Instantiate the Unit Under Test (UUT)
   uut: UShift PORT MAP (
          clk => clk,
          il => il,
          ir => ir,
          s => s,
          i => i,
          q => q);

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin        
   ---- test clr
      ir<= '0'; 
      wait for 40ns;
   ---- test parallel loading
        ir<= '1';
        s<= "11";
        i<= "0010";
        wait for 40ns;
     ---- test shift right
        s<= "01";
        il<='1';
    wait;   
   end process;
END;

Answer 1

是。以下是UShift的实体：

ENTITY UShift IS
 PORT(clk, il, ir : IN BIT;
 s: IN BIT_VECTOR(1 DOWNTO 0);
 i : IN BIT_VECTOR(3 DOWNTO 0);
 q : OUT BIT_VECTOR(3 DOWNTO 0));
END UShift;

以下是UShift_test中的相应组件：

COMPONENT UShift
PORT(clk : IN  std_logic; il : IN  std_logic; ir : IN  std_logic; i : IN  std_logic_vector(3 downto 0); s:IN std_logic_vector(1 downto 0); 
q : OUT  std_logic_vector(3 downto 0));
END COMPONENT;`:

如你所见，它们是不同的。除非您将配置与端口映射一起使用，其中包含类型转换函数，否则组件和实体应该完全相同。我强烈建议您不要尝试使用配置修复此问题，而是建议您更改要匹配的类型。您在设计中使用了BIT类型，这很不寻常。除非有充分的理由，否则我会将类型BIT更改为STD_LOGIC（以及相应的向量）。

而且，为什么要使用组件实例化？ 直接实例化更容易，输入更少，并且通常不需要组件实例化提供的额外灵活性。以下是比较两种方法的示例：https://www.edaplayground.com/x/2QrS。

实体与组件端口不匹配

1 个答案: